The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area effici...

This paper gives a summary of the wavelet transform for both continuous and time discrete signals. An algorithm for an effective computation of the DWT, namely the Mallat Algorithm, is described in greater detail. Its implementation with FIR filters can be optimized by applying the lifting scheme. This can extremely reduce the computational complexity. Some possible architectures that map the M...

Four types of VLSI architectures for the hardware realization of the FLOS-CM algorithm are introduced in this paper. Each architecture is appropriate for a particular environment. The FLOS-CM algorithm is found to be amenable for implementation using logarithmic arithmetic. A logarithmic architecture is shown to require up to 50% less area and be 14% faster than a linear fixed-point arithmetic ...

The grid and the mesh of trees (or MOT) are among the best-known parallel architectures in the literature. Both of them enjoy eecient VLSI layouts, simplicity of topology, and a large number of parallel algorithms that can eeciently execute on them. One drawback of these architectures is that algorithms that perform best on one of them do not perform very well on the other. Thus there is a gap ...

To realize a secure networking infrastructure, the author is carrying out CUE (Coordinating Users’ requirements and Engineering constraints) project with a network carrier and a VLSI manufacture. Since CUE-series data-driven processors developed in the project were specifically designed to be an embedded programmable component as well as a multi-processor element, particular design consideratio...

The continuous progress in semiconductor VLSI technologies during the past several decades has provided the opportunity of realizing real-time intelligent image processing systems such as image recognition, object tracking, motion recognition, etc. However, the traditional approach of running image processing algorithms on general purpose processors is not practical for building efficient syste...

Systolic arrays are a family of parallel computer architectures capable of using a very large number of processors simultaneously for important computations in applications such as scientific computing and signal processing. Systolic array architecture has contains 1 full adder and the latency with m per cell while semi-systolic array architecture has contains m/2 latency. The proposed multipli...

Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to...

Integrated Systems Group is focused on several key design aspects of modern integrated systems. The group is focused on building cutting edge, energy-efficient integrated systems through vertical optimization encompassing communications and signal processing algorithms and architectures, and digital and mixed-signal circuits. The main research topics include modeling of noise and dynamics in ci...

In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mea...