An arithmetic or with-carry analog of Blahut’s theorem is presented. This relates the length of the smallest feedback with carry shift register to the number of nonzero classical Fourier coefficients of a periodic binary sequence.

Instruction set design is a crucial aspect of computer architecture. The requirements to fulfill have evolved along time. For superscalar processing the most important feature is to avoid code coupling caused by data dependencies. However, instruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism for which it is important to ana...

Return-Oriented Programming (ROP) is a sophisticated exploitation technique that is able to drive target applications to perform arbitrary unintended operations by constructing a gadget chain reusing existing small code sequences (gadgets). Existing defense mechanisms either only handle specific types of gadgets, require access to source code and/or a customized compiler, break the integrity of...

This paper presents an obstruction-free solution to the (n, k)-set agreement problem in an asynchronous anonymous read/write system using solely (n− k+ 1) registers. We then extend this algorithm into (i) a space-optimal solution for the repeated version of (n, k)-set agreement, and (ii) an x-obstructionfree solution using (n− k + x) atomic registers (with 1 ≤ x ≤ k < n). 1 Context & motivation...

The TPM is a fairly passive entity. As a result, it can be difficult to involve the TPM in measurements of software trustworthiness beyond simple load-time hashing of static program code. We suggest an approach to dynamic, runtime measurement of software trustworthiness properties as they relate to code-data owernship relationships. We outline a system, SegSlice, that actively involves the TPM ...

Cog adds a just-in-time compiler for x86 to the existing interpreter. At this stage in its evolution Cog produces a VM that runs language-intensive (rather than library intensive) benchmarks from the computer language shootout [2] at around 5 times faster than the interpreter. While Cog’s code generation and message send optimization techniques are not novel, its plumbing of an x86 simulator in...

This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional unit usage and the micro operation level parallelism (MLP), which together determine the proper functional unit allocation for superscalar microprocessors, such as the x86 microprocessors. The proposed techniques fit in the early design exploration phase in which the t...

The control system of the 1.5 MeV FEL injector is built on the base of ported EPICS. It uses low-cost hardware: personal computers with the processor Intel x86 and CAMAC equipment produced by our institute. At present time, the distributed control system includes one Pentium at OPerator Interface (OPI) level and two IOC (Input Output Controllers) under supervision of the real time operating sys...