In the present work, results of a survey wheat crops in area IASS "Obraztsov chiflik" – Ruse are presented. The study was carried out during period 2018-2021, at experimental field institute, according to accepted methods for weed infestation, species composition entomofauna and economically important diseases. aim is determine weeds, diseases insect pest under relevant agro-climatic conditions...

Behavioral design helps the designer to understand the design space and subsequently coming up with a design that meets all the constraints specifically in a field programmable gate array (FPGA) based design paradigm. In this paper we have reported a novel design framework for creation of behavioral design. We have examined the opportunities brought about by finite state machines and to harness...

The paper suggests a technique, which permits to describe modular, hierarchical and parallel algorithms in Handel-C. This opportunity has been provided by generating the required control sequences with the aid of a hierarchical finite state machine. The proposed specification in Handel-C is synthesizable and it can be translated (for example, in DK2 environment of Celoxica) to EDIF format. The ...

This study aimed to reveal the diversity of aphid species and aphid-plant interactions adjacent Çardak Lagoon, which is close agricultural areas in Çanakkale Province Turkey. Twenty-seven belonging 17 genera three subfamilies from Aphididae (Hemiptera) were identified. Of these, Staticobium latifoliae (Bozhko, 1950) new record genus Mordvilko, 1914 Aphis symphyti Schrank, 1801 are records for f...

We consider the suitability of three types of language for the implementation of image processing algorithms on FPGAs; Hardware Description Languages, Parallel Language Extensions, Serial Language Extensions. We discuss the requirements for a language for this purpose and identify the weaknesses of four specific languages, VHDL, SystemC, Handel-C, SA-C and Match. Finally, we propose VERTIPH, a ...

Handel-C is a convenient tool for high-level design for FPGAs. Platform FPGAs, with high-levels of integration are suitable as packet processing devices. An existing ATM packet-switching design has been augmented with a CAM, with a simplified control structure, by the addition of a back-pressure mechanism, and a new shared-memory buffering scheme. The paper gives details of the Handel-C impleme...

This paper discusses the semantics of the prialt construct in HandelC[1]. The language is essentially a static subset of C, augmented with a parallel construct and channel communication, as found in CSP. All assignments and channel communication events take one clock cycle, with all updates synchronised with the clock edge marking the cycle end. The behaviour of prialt in Handel-C is similar in...