Many ASIC companies make it easy to add a PLL, offering the core as a drop-in cell on a standard-cell design or as a cell option in a gate array. However, that seemingly simple addition of a PLL cell to an all-digital ASIC can cause several problems if the ASIC designer isn’t careful. Although much of what is inside a PLL circuit is high-speed digital circuitry, the guts of the PLL include anal...

An integral part of the IBM eServer z990 I/O subsystem is the self-timed interface (STI) switch chip. The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system. The complexity of the functional verification of the STI switch chip is inherent in the implementation of seventeen logical clock domains and the s...

Current high-speed packet switching systems, ATM in particular, have large port bu ering requirements. The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics is facing a technology mismatch in the sense that today's chip technology does not allow to integrate on-chip the high-speed switching fabric with the large bu ering requirements. Consequent...

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors ...

In this paper, we investigate the application of concurrent error detection circuitry to a compact application-specific integrated circuit (ASIC) implementation of the Advanced Encryption Standard (AES). The specific objective of the design is to develop a method suitable for compact ASIC implementations targeted to embedded systems such that the system is resistant to fault attacks. To provide...

Transistor scaling has allowed a large number of circuits to be integrated into integrated circuit (IC) chips implemented in nanometer CMOS technology nodes. However, dark silicon which signifies for under-utilized circuitry will become dominant in future chips due to limited thermal design power (TDP). Furthermore, large voltage loss due to complex routing and placement will also degrade the p...

IC design is in a revolutionary phase at present. It could even be said that IC design is at the beginning of a new epoch. Design is moving toward nano-size. Thus, design techniques are advancing so rapidly that existing design knowledge quickly becomes obsolete. The IC design industry needs engineers with an integrated design perspective, real hands-on experience and well developed skills in p...

Application specific full custom design integrated circuit is a methodology for making a logic cell, circuit or layout specification. Full custom design circuit is the part of Application specific integrated circuit. A gate array or uncommitted logic array as an approach to the design and manufacture of application specific integrated circuit. It requires custom chip fabrication using a complet...

This paper presents a new undergraduate laboratory oriented to digital circuit design training based on Field Programmable Gate Arrays (FPGAs). The target of the course has been to introduce concepts of ASIC design methodology using a low cost alternative and a design-oriented, hands-on learning approach. FPGAs have permitted us to implement a massive VLSI-like design course, not only for futur...

Employment of highly integrated ASIC front-end electronics in GSI and FAIR detector systems is crucial in view of current and future detector granularity, overall channel number and radiation length to be minimized. Yet, integration of such multi-channel readout chips into detectors brings a severe technological gap up to light, where channel pitch on silicon is found on the order of 50 μm, whe...