Despite the computational complexity of cryptographic algorithms, physical implementations of secure hardware leak information an attacker can use to determine sensitive data. Data-dependent power consumption is one example of leaked information that can reveal an algorithm’s secret key through a Differential Power Analysis (DPA) attack. Dual-rail asynchronous circuits have been proposed as a c...

Sequential tasks cannot be effectively handled in logic programming based on classical logic or linear logic. This limitation can be addressed by using a fragment of Japaridze’s computability logic. We propose SeqWeb, an extension to LogicWeb with sequential goal formulas. SeqWeb extends the LogicWeb by allowing goals of the form G∧s G and G∨s G where G is a goal. These goals allow us to specif...

Modern technological processes for producing VLSI circuits have created an opportunity to exploit the advantages of asynchronous circuits. Compared to their synchronous counterparts, asynchronous circuits have the potential for lower power consumption, offer greater design flexibility, exhibit average rather than worst-case performance and have no problem with clock skew [Lav93, Hauck95]. Async...

To implement a linearizable shared memory in synchronous message-passing systems it is necessary to wait for a time linear to the uncertainty in the latency of the network for both read and write operations. Waiting only for one of them suffices for sequential consistency. This paper extends this result to crash-prone asynchronous systems, proposing a distributed algorithm building a sequential...

It has been proved that to implement a linearizable shared memory in synchronous message-passing systems it is necessary to wait for a time proportional to the uncertainty in the latency of the network for both read and write operations, while waiting during read or during write operations is sufficient for sequential consistency. This paper extends this result to crash-prone asynchronous syste...

This paper presents a novel modeling called stacked timeasynchronous sequential networks (STASNs) for online endof-turn detection. An online end-of-turn detection that determines turn-taking points in a real-time manner is an essential component for human-computer interaction systems. In this study, we use long-range sequential information of multiple time-asynchronous sequential features, such...

VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In ...

The test generation problem for a sequential circuit capable of generating tests with combinational test generation complexity can be reduced to that for the combinational circuit formed by replacing each FF in the sequential circuit by a wire. In this paper, we consider an application of this approach to general sequential circuits. We propose a test generation method using circuit pseudo-tran...

This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ...

A Gals (Globally Asynchronous Locally Synchronous) system typically consists of a collection of sequential, deterministic components that execute concurrently and communicate using slow or unreliable channels. This paper proposes a general approach for modelling and verifying Gals systems using a combination of synchronous languages (for the sequential components) and process calculi (for commu...