This paper presents results of a design that uses CMOS current mode logic that can be used to implement the high precision, speed critical elements of the mixed-signal systems. The design is based upon the 0.25-μm CMOS TSMC process. The propagation delays of the new current mode logic are compared to those of equivalent gates implemented in conventional CMOS logic. The results show a propagatio...

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal–oxide–semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digit...

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and ...

The design of a CMOS operational mirrored amplifier (OMA) suitable for high frequency applications is proposed. The CMOS operational mirrored amplifier is developed using class AB operational amplifier and two current mirrors. To obtain a wide bandwidth and high stability, HF feedforward techniques have been used. These techniques made the proposed circuit suitable for continuous – time analog ...

This paper shows a new approach to low-power low-voltage CMOS MultipleValued (MVL) Ternary Logic, the “complete model”. This logic uses standard technology processes and requires only an extra power supply more than binary CMOS circuits. Using an original characterisation of CMOS multivalued dynamic gates, it is shown as the advantages obtained are better noise margins and a lower power consump...

This paper analyses two front-end receiver architectures intended for GSM900 use; (i) A direct-conversion receiver, and (ii) a low-IF receiver using a poly-phase filter. The aim is to determine the circuit performance required for GSM operation and to compare this to current state-of-the-art CMOS performance. The analysis shows that direct-conversion receivers fail to meet specifications when b...

−A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed struct...

The advent of CMOS micromachining has introduced new design rules for fabrication of integrated CMOS-MEMS devices. This paper presents a context dependent DRC algorithm to handle the issues related to pre-fabrication verification of such layouts. In addition, problems related to density control, specific to CMOS-MEMS designs, are discussed. An automatic slotter which introduces MEMS-compatible ...

This paper proposes a novel 8-phase VCO design implemented using Carbon Nanotube Field-Effect Transistors (CNTFETs). Carbon Nanotube is a fast growing and promising technology to replace Traditional MOSFETs. Its operation principles and device structure are similar to the conventional bulk CMOS, however it shows a great power delay improvement over bulk MOSFET due to its near-ballistic CNT tran...

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modelin...