This paper describes a two-stage method to generate test sets for I testing and to determine the leakage DDQ fault coverage for given test pattern sets. The method has been integrated within a fault simulator. Furthermore, it will be proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a static CMOS circuit if the ...

Abstract As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. This paper reports a novel design technique which aids in the reduction of switching noise. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driv...

In this paper, design, implementation and characterization of a 3-V switched-capacitor (SC) CMOS interface circuit for the closed-loop operation of a lateral capacitive microgravity silicon-on-insulator (SOI) accelerometer is presented. The interface circuit is based on a front-end programmable referencecapacitorless SC charge amplifier and a back-end second-order SC modulator. The acceleromete...

Here we describe a multi-compartment neuron circuit based on the Adaptive-Exponential I&F (AdEx) model, developed for the second-generation BrainScaleS hardware. Based on an existing modular Leaky Integrate-and-Fire (LIF) architecture designed in 65 nm CMOS, the circuit features exponential spike generation, neuronal adaptation, inter-compartmental connections as well as a conductance-based res...

ICID (Integrated Circuit IDentification) is a small mixed-signal cell that can be added to the test logic on a CMOS integrated circuit. It provides a unique 224 bit identification number that can be accessed during die test. This identification can be used to correlate test information for individual die on the wafer, through package test, and into the field and back. The identification bits ar...

Researchers at Oak Ridge National Laboratory (ORNL) are developing selectively coated cantilever arrays in a surface-micromachined MEMS process for very high sensitivities in chemical and biological sensing. Toward this end, we have developed a one-dimensional (1-D) 10-element microcantilever array that we have coated with gold for mercury sensing and palladium for hydrogen sensing. Ultimately ...

A compact integrated CMOS circuit for temporal differentiation is presented. It consists of a high-gain inverting amplifier, an active non-linear transconductance and a capacitor and requires only 4 transistors in its minimal configuration. The circuit provides two rectified current outputs that are proportional to the temporal derivative of the input voltage signal. Besides the compactness of ...

This paper presents hardware implementation of the data encryption and decryption of the DES standard algorithm. The design consists of the S-Box circuit Exclusive-OR circuit, Circular Left Shift circuit and the control unit. The S-Box circuit implemented using 32 PLDs (Programmable Logic Device) chip that hold substitution a 48-bits input data and yields a 32-bits output data. The other circui...

The structures that can be implemented and the materials that are used in complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology are optimized for electronic performance. However, they are also suitable for manipulating and detecting optical signals. In this paper, we show that while CMOS scaling trends are motivated by improved electronic performance, they are also c...

The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated anten...