This paper gives important features of CMOS and BiCMOS four-diodes direct coupled tuneable resistance. Circuit performances of three resistance topologies are explored and compared with the traditional CMOS tuneable transresistance designed from a one-stage operational transconductance amplifier (OTA). Simulations results have been realised using nominal parameters of the AMS 0.8μm CMOS and BiC...

This paper presents the first 150GHz amplifier in a digital 65nm CMOS technology. Design techniques to preserve raw transistor gain near fmax include layout optimization, dummy-prefilled microstrip lines (MSL) for design-rule compliance, and matching topologies which minimize passive element losses. To the authors’ knowledge, the measured 8.3dB gain, 6.3dBm saturated output power (Psat), 1.5dBm...

This paper presents a brief introduction of some prominent current mode circuits which have been finding its attention in the area of analog signal processing. High performance current differencing transconductance amplifier (CDTA) has been realized using CMOS, provides a wider bandwidth, low power consumption and requires less space in integrated circuits implementation. Pspice simulation resu...

This paper presents results of investigation on the effects of technology on the performance of the class E power amplifier circuit. A typical class E circuit has been designed and simulated, for a typical UMTS Tx frequency (1.95 GHz) and output power ( 27dBm). Three different technologies have been used (silicon BJT, CMOS and GaAs HBT) and several important parameters (output efficiency, power...

Abstract A hybrid switching amplitude modulator for class-E2 EDGE polar transmitters is proposed. To achieve both high-efficiency and high-speed, it consists of a wideband buffered linear amplifier as a voltage source and a hysteresis-controlled switching amplifier as a dependent current source. The novel linear amplifier has a high current driving capability of approximately 160mA with a bandw...

This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b low-power 0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC capacitor mismatch wh...

A 1.2 V, 0.61 mA bias current, low noise amplifier (LNA) suitable for low-power applications in the 2.4 GHz band is presented. Circuit has been implemented, laid out and simulated using a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB power gain a noise figure NF< 2.28 dB and a 1-dB compression point of −15.69 dBm, while dissipating 0.74 mW. Such performance make this design suita...

ETRI Journal, Volume 29, Number 5, October 2007 ABSTRACT⎯An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-μm CMOS process and adopts a twostage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are m...

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35μm CMOS technology, the ΣΔ modulator achieves 86 ...