In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak ...

Two new techniques for mapping circuits are proposed in this paper. The rst method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS/PTL method, uses a mix of static CMOS ...

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the a...

The trade-offs between bandwidth, resolution and power in high dynamic range pipeline analog-to-digital converters are studied when a pure digital CMOS technology is considered. Calibration techniques are presented to achieve the required resolution, and the design optimization methodology of the relevant pipeline building blocks are discussed. An example of a 15-b 10Ms/s analog-to-digital pipe...

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary...

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, ...

This paper reviews (a) recent CMOS demonstrations of capabilities for Radio Frequency (RF), microwave, and millimeter wave circuits from 1 GHz to 100 GHz, (b) advances in on-die isolation structures for integrating radio’s delicate circuits with very noisy general-purpose processors on the same die, and (c) entirely novel design methods for complex RF passive networks on the package substrate b...

As technology scales down into the nanometer region, the reliability mechanism caused by time dependent dielectric breakdown (TDDB) has become one of the major reliability concerns. TDDB can lead to performance degradation or logic failures in nanoscale CMOS devices, and can cause significant increase of leakage power in the standby mode. In this paper, the TDDB effects on the delay and power o...

The two major things, size and power consumption are very important parameter for any digital circuit design. Because all of us want to use the equipments that have compact in size and less power consumption, this paper investigates the applications of CMOS technology in the nanometer regime beyond 20 nm channel length where the relative study of average power dissipation of CMOS inverter is fo...