" In his heart a man plans his course, but the LORD determines his steps.... " – Proverbs 16:9 To my parents iii ACKNOWLEDGMENTS During my Ph. D. study, there are many people in Georgia Tech to whom I am thankful. First of all, I would like to express enormous appreciation to my adviser, Dr. Vincent J. Mooney III, from the bottom of the heart. In addition to his enthusiasm and professionalism d...

Crossbar-based switches are commonly used to implement routers with throughputs up to about 1 Tb/s. The advent of crossbar scheduling algorithms that provide strong performance guarantees now makes it possible to engineer systems that perform well, even under extreme traffic conditions. Until recently, such performance guarantees have only been developed for crossbars that switch cells rather t...

A reconfigurable parallel architecture whose interconnection topology can be dynamically modified in order to match the communication characteristics of a given algorithm provides flexibility for efficient execution of various applications. But, due to communication links switching devices design constraints, connecting a large number of processors on a dynamically programmable interconnection ...

We present Hipernetch, a novel FPGA-based design for performing high-bandwidth network switching. FPGAs have recently become more popular in data centers due to their promising capabilities wide range of applications. With the recent surge transceiver bandwidth, they could further benefit implementation and refinement switches used centers. Hipernetch replaces crossbar with “combined parallel r...

Partial reconfiguration offers several benefits for a system on chip. But in order to take advantage of this technique, easy access and low overhead must be provided. One key issue therefore is the on-chip communication architecture. Current reconfigurable systems use buses and fixed links, which are quite inflexible; recent proposals suggest using networks on chip instead. The problem of the l...

In this paper, packet loss probability performance in cell-based and packet-based switches with finite Input Queues (IQ) and iLPF scheduling algorithm are analysed. This algorithm has been proposed as a practical scheduling algorithm to achieve 100% throughput in cell-based switches. The scheduling algorithm is implemented in three cases: cellbased (CB-iLPF) switching, packet-based (PB-iLPF) sw...

We study the provision of deterministic rate guarantees over single crossbar switches. Birkhoff decomposition yields a general approach for this problem, but the required complexity can be very high and the quality of service can be unsatisfactory for practical traffic sources. We develop a method called rate quantization which converts the set of desired rates into a certain discrete set in su...

This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a...

Future interconnection networks will be required to achieve ultra-high bandwidth and low latency communications to cope with the increasing performance requirements of backbone routers, large data storage systems and supercomputing systems. Aiming at achieving ultra-high bandwidth communications and approaching optical time-of-flight processing latency while being robust to cascade impairments,...