In addition to traditional manufacturing test, today’s yield optimization procedures for very deep submicron chips necessitate the use of test technology. These procedures are meant to ensure the manufacturability of the chips and to achieve adequate levels of yield and reliability. This position statement summarizes the key trends and challenges resulting in manufacturing susceptibility and fi...

This paper presents a novel approach to formulating compact I−V models for deep-submicron MOS technology development. The developed model is a one-region closedform equation that resembles the same form as the longchannel one, which covers full range of channel length and bias conditions. Model parameter extraction follows a oneiteration prioritized sequence with minimum measurement data, and c...

In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode inter...

As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. This paper explores the impacts of random and systematic process variations on SRAM cell stability and timing. The largest contributors to these robustness and timing ...

In this work, a simple and effective way to modify the support surface is developed and a nanostructure ceramic support to facilitate deposition of a defect-free overlying micro and meso (nano) porous membrane is obtained. To achieve high performance nanocomposite membranes, average pore size of outer surface of support was reduced by dip-coating in submicron and nano α-alumina slurries. In...

Advances in semiconductor technologies, and the aggressive time-to-market, performance, and cost requirements have led to a paradigm shift in electronic system design, with the evolution of system-level-integration allowing an entire system to be integrated on a single chip. At the same time, the applications which stand to benefit most from the use of embedded system-on-chips, like portable te...

An accelerated wear-out of ultra-thin gate oxides used in contemporary deep-submicron CMOS technologies is one of the effects observed in MOSFETs submitted to irradiation with high LET particles [1-5]. The damage introduced in the gate oxide by an impinging ion may in fact act as a seed for further degradation produced by electrons and holes injected at high fields during a subsequent electrica...

INTRODUCTION This paper analyses the ability of single-photon avalanche diodes (SPADs) for neural imaging. The current trend in the production of SPADs moves toward the minimum dark count rate (DCR) and maximum photon detection probability (PDP). Moreover, the jitter response which is the main measurement characteristic for the timing uncertainty is progressing. METHODS The neural imaging pro...

Sixty percent of the world ocean by area is contained in oligotrophic gyres [Longhurst A (1995) Prog Oceanog 36:77-16], the biomass of which is dominated by picophytoplankton, including cyanobacteria and picoeukaryotic algae, as well as picoheterotrophs. Despite their recognized importance in carbon cycling in the surface ocean, the role of small cells and their detrital remains in the transfer...

− Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metr...