In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In ...

Skyrmion-based devices are promising candidates for non-volatile memory and low-delay time computation. Many skyrmion-based execute operation by controlling skyrmion trajectory, which can be impeded the Hall effect. Here, design of arithmetic built on synthetic antiferromagnetic (SyAF) structures is presented, where structure greatly suppress In this study, operations half adder, full XOR logic...

Releasing the stringent accuracy requirement would potentially offer greater freedom to create a design with better performance or energy efficiency. In this paper, we evaluate the design trade-offs for adders, which are key building blocks for many applications. We demonstrate the optimum design metric for adders, under the consideration of various design constraints, such as accuracy, operati...

Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...

We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 µm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second circuit is an asynchronous adder, which uses the...

Abstract. High-speed MARS encryption/decryption hardware was developed using a 0.18μm IBM CMOS technology. In order to boost performance, a special adder and multiplier was designed by optimizing the adder block structure and interconnections between adder cells using signal delay profiles. A description of the hardware including block diagrams and data flow diagrams is presented. One of the mo...

In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs) are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold) are used. First design generates SUM a...

Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...