Wavelength accuracy and stability are key requirements for differential absorption lidar (DIAL). We present a control and timing design for the dual-stabilized cw master lasers in a pulsed master-oscillator power-amplifier configuration, which forms a robust low-cost water-vapor DIAL transmitter system. This design operates at 823 nm for water-vapor spectroscopy using Fabry-Perot-type laser dio...

In the title compound, {[Cu(C(9)H(15)N(13))(2)](ClO(4))(2)}(n), the Cu(2+) cation lies on an inversion center and is coordinated by the tetra-zole N(4) atoms of six symmetry-equivalent tris-[2-(1H-tetra-zol-1-yl)eth-yl]amine ligands (t(3)z) in the form of a Jahn-Teller-distorted octa-hedron with Cu-N bond distances of 2.0210 (8), 2.0259 (8) and 2.4098 (8) Å. The tertiary amine N atom is stereoc...

A 4 GHz PLL (phase-locked loop)-type frequency synthesizer has been implemented in the standard 0.18μm mixed-signal and RF 1P6M CMOS technology. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are...

A two-axis optical imaging system using a Lissajous scan pattern with non-integer frequency ratio is presented. A waveguide with precisely tuned mechanical resonant frequencies is constructed by dip coating two fibres with a transparent polymer. Motion is achieved by mounting a waveguide cantilever at 45° on a single piezoelectric actuator with a dual-frequency drive. Confocal signal collection...

A DLL(Delay Locked Loop) with DCC(Duty Cycle Correction) has become an essential block in high speed memory and digital circuits. An SMD(Synchronous Mirror Delay) structure is widely used both for skew reduction and for DCC. In this paper, an area-efficient DLL structure based on the merged dual SMD is proposed. The merged structure allows the forward delay array to be shared between the DLL an...

Delay-locked loops are an attractive alternative to VCO-based phase-locked loops due to their simpler design and inherent stability [1-3]. The primary disadvantage of conventional DLLs is limited phase range, that limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating range. T...

This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 μm standard CMOS process with a 3.3 V supply voltage. The...

Delay locked loops are an attractive alternative to VCO based phase locked loops due to their simpler design and inherent stability [1]-[3]. The primary disadvantage of conventional DLLs is their limited phase range, which limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating...