This paper presents a novel approach to memory power optimization for embedded systems based on the exploitation of data locality. Locations with highest access frequency are mapped onto a small, low-power application-speci c memory which is placed close the processor. Although, in principle, a cache may be used to implement such a memory, more e cient solutions may be adopted. We propose an ar...

Due to their tight memory constraints, small microcontroller based embedded systems have traditionally been implemented using lowlevel languages. This paper shows that the Scheme programming language can also be used for such applications, with less than 7 kB of total memory. We present PICOBIT, a very compact implementation of Scheme suitable for memory constrained embedded systems. To achieve...

We study embedded Binarized Neural Networks (eBNNs) with the aim of allowing current binarized neural networks (BNNs) in the literature to perform feedforward inference efficiently on small embedded devices. We focus on minimizing the required memory footprint, given that these devices often have memory as small as tens of kilobytes (KB). Beyond minimizing the memory required to store weights, ...

the problem discussed in this paper is the effect of latency time on the ogy chaos control methodology in multi chaotic systems. the smith predictor, rhythmic and memory strategies are embedded in the ogy chaos control method to encounter loop latency. a comparison study is provided and the advantages of the smith predictor approach are clearly evident from the closed loop responses. the comple...

AbscrocrWe present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 x 128 vector-matrix multiplier on a single 3 mm x 3 mm ch...