Quantum error correction and fault-tolerant quantum computation are two fundamental concepts which make quantum computing feasible. While providing a theoretical means with which to ensure the arbitrary accuracy of any quantum circuit, fault-tolerant error correction is predicated upon the robust preparation of logical states. An optimal direct circuit and a more complex fault-tolerant circuit ...

Magic state distillation is a fundamental technique for realizing fault-tolerant universal quantum computing, and produces high-fidelity Clifford eigenstates, called magic states, which can be used to implement the non-Clifford π/8 gate. We propose an efficient protocol for distilling other non-stabilizer states that requires only Clifford operations, measurement, and magic states. One critical...

In the multi-peta-flop era for supercomputers, the number of computing cores is growing exponentially. However, as integrated circuit technology scales below 65 nm, the critical charge required to flip a gate or a memory cell has been dangerously reduced, causing higher cosmic-radiations-induced soft error rate. Soft error threatens computing system by producing silently data corruption which i...

The growing number of circuits implemented in Field Programmable Gate Arrays (FPGAs) and the increased susceptibility, due to higher integration levels, of these devices to soft faults caused by radiation at ground level is leading the scientific and technical community to the study of new fault tolerant designs and solutions, and how they can be verified and validated. Using fault injection te...

On-chip Built-In Self-Test (BIST) based diagnosis of the embedded Field Programmable Gate Array (FPGA) core in a generic System-on-Chip (SoC) is presented. In this approach, the embedded processor core in the SoC is used for reconfiguration of the FPGA core for BIST, initiating the BIST sequence, retrieving the BIST results, and for performing diagnosis of faulty programmable logic blocks, memo...

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic G...

There is a need for better integration of the fault tolerant and the control designs for safety critical systems such as aircraft. The dependability of current designs is assessed primarily with measures of the interconnection of fault tolerant components: the reliability function and the mean time to failure. These measures do not directly take into account the interaction of the fault toleran...

Replication is widely used to improve fault tolerance in distributed and multi-agent systems. In this paper, we present a different point of view on replication in multi-agent systems. The approach we propose is based on role concept. We define a specific “fault tolerant role” which encapsulates all behaviors related to replication-based fault tolerance in this work. Our strategy is mainly focu...

In this work we study a new approach of fault tolerant control schema.The suggested strategy is an active Fault Tolerant Control (FTC) strategy that reconfigures the controller on-line taking into account changes due to the faults where both the block of fault detection and the block of the controller are formulated as a Linear Matrix Inequality (LMI) problem. The problem of fault estimation is...

The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant over...