Problem statement: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. Approach: This study presented on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach ...

Many applications invoke the Fast Fourier Transform (FFT) on sparse inputs, with most of their Fourier coefficients being very small or equal to zero. Compared with the “dense” FFT algorithms, the input sparsity makes it easier to parallelize the sparse counterparts. In general, sparse FFT algorithms filter input into different frequency bins, and then process the bins separately. Clearly, the ...

• We compute estimates of inefficiency when its distribution is unknown in Stochastic Frontier Models (SFMs) and Data Envelopment Analysis (DEA). Our procedure based on the Fast Fourier Transform (FFT) utilizes empirical characteristic function. The new techniques perform well Monte Carlo experiments. They deliver reasonable results an application to large U.S. banks. Deconvolution DEA scores w...

Abstract – The Fast Fourier Transform (FFT) is a critical part in communication systems, because it can greatly reduce the computation requirement for signal processing. This paper presents the design of a FFT processor using NULL Convention Logic (NCL), which has been shown to have power consumption advantages over its synchronous counterpart. Performance metrics for the NCL FFT processor are ...

It was decided to implement the FFT on GLiTCH because it is both a useful routine for image processing and also very computationally demanding. When implemented on an array processor, the FFT serves as a good test of the mathematic and data movement capabilites of the machine. Given that GLiTCH is restricted on memory size, and is also only a pseudo-2D array, it was felt that the 2D FFT would s...

In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double proces...

In this paper, a scaling method for large pipelined FFT implementations is proposed. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor is implemented in a 0.35μm standard CMOS technology and is capable of calculating a 2048 complex point FFT or IFFT in 40μ...

Transport Triggered Architecture (TTA) offers a cost-effective tradeoff between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complexvalued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FF...

SVD and FFT are both the efficient tools for image analysis and face recognition. In this paper, we first study the role of SVD and FFT in both filed. Then the decomposition information from SVD and FFT are compared. Next, a new viewpoint that the singular value matrix contains the illumination information of the image is proposed and testified by the experiments based on the ORL face database ...