This paper presents the design and implementation of image processing applications on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. Two FPGA-based architectures for image processing have been proposed: Color Space Conversion and Edge Dete...

Abstract—This paper analyzes the experimental investigation of indirect field oriented control of Field Programmable Gate Array (FPGA) based five-phase induction motor drive. A detailed d-q modeling and Space Vector Pulse Width Modulation (SVPWM) technique of 5-phase drive is elaborated in this paper. In the proposed work, the prototype model of 1 hp 5-phase Voltage Source Inverter (VSI) fed dr...

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central f...

A biometric system based on the iris recognition is especially an attractive approach for user identification. Implementation of the iris recognition algorithm on FPGA (field programmable gate array) achieving significant reduction in execution time when compared with software implementation. This paper takes a review on selected methods on research of different methods used for Hardware implem...

A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design is carefully matched with features of the FPGA architecture, utilizing embedded 18×18-bit multipliers on the FPGA and employing a carry save addition scheme. Using this architecture, a 1024-bit modular exp...

Recently, computer architectures that combine a reconng-urable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of ne grain par-allelism in applications. In this paper, we study the performance of the reconngurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (...

Recently, computer architectures that combine a recon gurable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of ne grain parallelism in applications. In this paper, we study the performance of the recon gurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (FP...

A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardwar...

In this paper, we present a configurable FPGA-based hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed pipelined architecture...

Today, real-time processing has become a stipulation in all practical fields especially in image processing. This paper presents an experimental comparison of implementation of Niblack’s Algorithm, a binarization algorithm for image-processing in Visual C++ using OpenCV library with its implementation on FPGA. It aims at addressing the real-time processing scenario and how to overcome the situa...