This paper presents the implementation of blushless DC (BLDC) motor control algorithm by using a Field Programmable Gate Array (FPGA) and the design of a fast responding BLDC motor drive circuit on an autonomous miniature quadcopter. The algorithm involves implementation of acceleration, deceleration, and equalization energy step change function in motor control the strategy. In order to design...

<p>Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) sistem penggerak motor yang membutuhkan perhitungan sangat cepat. Field Programmable Gate Array (FPGA) merupakan salah satu perangkat dapat digunakan implementasi komputasi memerlukan kecepatan dan presisi tinggi. Penerapan FPGA menggunakan metode digit by non-restoring de...

This paper is devoted to the design of a 258-bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients. Exploiting this splitting we designed a pipelined 65-bit multiplier base...

Quadratic Rotation decomposition (QRD) based recursive least squares (RLS) algorithm can be used in variety of communication applications and its low complexity implementation can be of interest. In this paper we have presented an application of QRD based RLS algorithm using Coordinate Rotation by Digital Computer (CORDIC) operator for implementing an adaptive beamformer. FPGA resource estimate...

Interconnections are increasingly one of the dominant contributors to delay, area and energy consumption in CMOS digital circuits now a days. Multiple Valued Logic (MVL) can decrease the average power required for level transitions and also the number of required interconnections are reduced. So the impact of interconnections on overall energy consumption is reduced. In this paper, a quaternary...

This paper describes a new reconfigurable analog array (RAA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithmdriven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environme...

In this paper, we present a new approach for real-time implementation of the Chen’s chaotic system on Field Programmable Gate Array (FPGA). The approach consists on using structural hardware description language (VHDL) with a fixed-point representation, contrary to some previous works which use somewhat non optimal VHDL code generation using automatic code generation tools. The obtained real-ti...

The FPGA (Field Programmable Gate Array) constitute of many programmable modules like Configuration Logic Blocks (CLBs), Block Random Access Memories (BRAM), DSP 48 blocks and Input/output (I/O) modules. The CLBs are the main programmable logic units which consist of different number of logic slices and each slice contains different number of LUTs and flips flops depending upon the FPGA device ...

ASIC Chips and Digital Signal Processors are generally used for implementing digital filters. Now days the advanced technologies lead to use of field programmable Gate Array (FPGA) for the implementation of Digital Filters.The present paper deals with Design and Implementation of Digital IIR Chebyshev type II filter using Xilinx System Generator. The Quantization and Overflow are main crucial p...

Application Specific Integrated Circuits (ASICs) and Digital Signal Processors are generally used for implementing digital filters. Now days in the advances in technology leads to use of field programmable Gate Array (FPGA) for the implementation of Digital Filters. The Present paper deals with Design and implementation of digital IIR Butterworth filter using Xilinx System Generator. The Quanti...