objective: to assess the level of awareness on breast cancer among women of reproductive age. materials and methods: a cross-sectional descriptive study was conducted in opd of dhaka medical college hospital among the 175 respondents by face to face interview using pretested semi structured questionnaire. results: one forth (23%) aged 21-25 years, mostly muslim (86.3%), housewives (72.57%), had...

An attractive and challenging way of constructing complex computing systems is their automated synthesis from a range of behavioural specifications. In this paper, we explore one particular instance of this approach which aims at constructing a GALS (globally asynchronous locally synchronous) system from its behavioural specification given in terms of a suitable transition system. More precisel...

This paper presents a new generic system architecture and design methodology for the design, debugging and testing of complex systems-on-chip (SoC). Starting from a hierarchical generic system architecture, platforms for dedicated application scenarios will be customized. In order to be able to handle very complex submicron designs, the system is based on a globally asynchronous and locally syn...

Today’s complex SOC solutions demand low power processors. Synchronous processors which consume conveniently replaced by low power delay-insensitive (DI) asynchronous logic. In this paper, a Micro-pipelined GALS based 2D Fast Fourier Transform [FFT] Processor is designed and implemented to perform power, area and timing analysis. The implemented design has given power advantage of 78.22% and ti...

This paper presents the design of a restartable crystal controlled clock. The clock generator is a critical component in a newly proposed blended design methodology which combines clockless and clocked subsystems and is a special case of a Globally Asynchronous Locally Synchronous (GALS) design strategy. The clock generator has been successfully implemented in the TSMC 0.25μm NWELL process, occ...

– In this paper, we introduce an efficient design flow for Globally Asynchronous Locally Synchronous systems, which can be used by designers without prior knowledge of asynchronous circuits. The design flow starts with a high-level description model of the system in Simulink and ends with a hardware implementation in an FPGA or a standard-cell ASIC. We have developed a tool in MATLAB, so that t...

This paper addresses the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. Pre-layout simulati...