It is well known that state encoding can in uence the logic initializability of an FSM implementation. If the sole objective of an \optimal" state assignment is to minimize the amount of logic, one may end up with implementations that are logically uninitializable. That is, a 3-valued (0,1,X) logic simulator may not be able to initialize the circuit even when its FSM has a synchronizing sequenc...

High Q frequency reference devices are essential components in many Integrated circuits. This paper will focus on the Resonant Suspended Gate (RSG) MOSFET. The gate in this structure has been designed to resonate at 38.4MHz. The MOSFET in this device has a retrograde channel to achieve high output current. For this purpose, abrupt retrograde channel and Gaussian retrograde channels have bee...

A learning algorithm is presented for circuits consisting of a single soft winner-take-all or k-winner-take-all gate applied to linear sums. We show that for these circuits gradient descent with regard to a suitable error function does not run into the familiar credit-assignment-problem. Furthermore, in contrast to backprop for multi-layer perceptrons this learning algorithm does not require th...

An important part of the design flow, technology mapping, expresses logic functions of the netlist using gates from the technology library, in the presence of various design constraints. This paper proposes a new approach to technology mapping, which relies on several known techniques, combined and tuned to work in a new way. The previous work on DAG mapping is extended, by proposing new method...

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

The Cameron project has developed a language called single assignment C (SA-C), and a compiler for mapping image-based applications written in SA-C to field programmable gate arrays (FPGAs). The paper tests this technology by implementing several applications in SA-C and compiling them to an Annapolis Microsystems (AMS) WildStar board with a Xilinx XV2000E FPGA. The performance of these applica...

We have studied the line shape and frequency of the G band Raman modes in individual metallic single walled carbon nanotubes (M-SWNTs) as a function of Fermi level (epsilonF) position, by tuning a polymer electrolyte gate. Our study focuses on the data from M-SWNTs where explicit assignment of the G- and G+ peaks can be made. The frequency and line shape of the G- peak in the Raman spectrum of ...

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

Context-based adaptive binary arithmetic coding (CABAC) is a very important entropy coding technique defined in H.264. It is not easy to store and retrieve efficiently the previously encoded syntax elements especially when full hardwired VLSI implementation of CABAC is required. This paper presents an efficient design of context modeler which uses the well-organized location-index assignment an...