Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight ca...

In any high-speed digital circuit, problems like clock skew, transmission delays and off-chip communication are worrisome. Being particularly fast, GaAs technology is a good candidate for global clock free design. In this paper, a detailed analysis of several differential-type structures and C-elements, used to build self-timed delay-insensitive circuits, is carried out by HSPICE simulations in...

filter output node and the other constitutes the additional observation point. Obviously, this point has to be judiciously chosen to be able to obtain an increase in fault coverage. So, the two analyser inputs are connected to (i) the output node of the fdter and (ii) the output node of the op-amp differential stage as shown in Fig. 2. The HSPICE fault simulations show that in this situation, o...

This paper presents a versatile current-mode circuit which combines the advantages of analog and digital techniques to perform long-term memory and computing functions. It is based on current-mode algorithm data converters and standard semistatic latches. Hspice simulations are included to illustrate its behavior. The design of the A/D subcell has been improved by using current injection techni...

In this paper an accurate method is presented for determining of the device sizes in a RF circuit based on genetic algorithm (GA). HSPICE RF simulation is used for evaluating of the fitness of the circuit specifications per every iteration of the GA. Also an example for a LNA is presented for evaluating of non-dominated sorting genetic algorithm (NSGA-II) as a method of multi objective genetic ...

Abstract: In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style. Simulated data for the logic style is presented and compared to related ULV logic styles and complementary CMOS gates. The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. In terms of energy delay product (EDP) the logic style offers a significant...

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect tr...

A Membership Function Generator Circuit (MFGC) with bias supply of 1.5 Volts and independent DCvoltage programmable functionalities is presented. The realization is based on a programmable differential current mirror and three compact voltage-to-current converters, allowing continuous and quasi-linear adjustment of the center position, height, width and slopes of the triangular/trapezoidal outp...

In order to perform mixed-domain simulation of electrically actuated bow-tie shaped doubly-fixed microbeams, a nodal model for the trapeziform beam and corresponding equivalent circuit are developed by HSPICE. The nonlinearities including mid-plane stretching and electrostatic forcing are considered. In the modeling, the Galerkin residual method is used to discretize the partial differential eq...

This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance monotonicity in random variations constraint maximization can be used to efficiently find critical constraints and worst-case scenarios of random process variations and populate them into a multi-scenario optimization. Thi...