In this paper, we introduce the design of an advanced high-performance interconnect architecture for supercomputers. first part consider generation Angara (Angara G1). The is based on router ASIC, which supports a 4D torus topology, deterministic and adaptive routing, has hardware support RDMA technology. interface with processor unit PCI Express. G1 extremely low communication latency 850 ns u...

The system-on-chip (SoC) design paradigm and deep submicron (DSM) technology bring two main challenges to the ASIC design community. The first one is productivity to use millions of gates within ever shorter time-to-market, which is currently tackled with the design methodology based on Intellectual Property Right (IPR) blocks. The second challenge is coping with rapidly changed technology para...

COMPUTING IN SCIENCE & ENGINEERING In the 20th century, mainstream electronics evolved from vacuum tubes and discrete copper wires to individual transistors and batch-fabricated, printed wiring boards to its current form, which integrates more than a billion transistors and copper interconnections in a single silicon chip. Until the past decade, designers benignly neglected the electrical perfo...

-Transient response of any system depends upon the initial conditions. In this paper a review on the transient response under various conditions is represented. Apart from the transient response this paper strives to represents a review of the effect of conductance on the delay under various technologies applied to interconnect field. Interconnects are the back bone to any high density chip. Al...

Fluidic interconnects provide the passages for the transport of liquid analytes, containing mass and information, from one component to another in a microfluidic system. The pressure capacity of a novel, modular, gasketless, chip-to-chip microfluidic interconnect that forms a seal with a liquid bridge suspended between concentric through-holes was evaluated experimentally (see Figure 1). [5] Th...

Cluster interconnect performance is typically characterized by latency and throughput. However, not only latency and throughput but also the CPU utilization of an interconnect are important attributes that affect overall system performance. In our studies, we have run cluster benchmarks with two device drivers with different throughput and latency characteristics. We have observed that point-to...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...

This article describes a novel Boundary Scan-like Built-In Self-Test (BIST) conception for autonomous at-speed testing and diagnosis of interconnect. It is based on recently proposed very efficient design of test pattern generation and response analysis hardware, which allows detection and diagnosis of both static and dynamic faults upon interconnects between chips in a multi-chip environment. ...

High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming much cheaper while wires are still expensive. Therefore, optimization efforts should focus on the wire resources. In this paper, we devise an objective function to balance the interconnect topology between routing are...

Process variation is considered to be a major concern in the design of circuits including interconnect pipelines in current deep submicron regime. Process variation results in uncertainties of circuit performances such as propagation delay. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be at...