We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline sil...

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene...

Polymer light-emitting transistor is realized by vertically stacking a top-emitting polymer light-emitting diode on a polymer space-charge-limited transistor. The transistor modulates the current flow of the light-emitting diode by the metal-grid base voltage. The active semiconductor of the transistor is poly 3-hexylthiophene . Yellow poly para-phenylene vinylene derivative is used as the yell...

High frequency models of transistors are of interest because they have applications to computeraided design of high frequency circuits. When these models are derived, a problem encountered is that measured transistor S-parameters do not agree with the hybrid-π model. In this article, a simplified method is described to obtain an optimized classical hybrid-π model that predicts the measured S-pa...

This brief proposes an analytical approach to model the DC electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistors (JL-NW-FETs). The includes explicit expressions, taking into account first-order perturbation theory for calculating eigenstates and corresponding wave-functions obtained by Schrödinger equation in cylindrical-coordinate. Assessment propos...

A method for collapsing the transistor chain of CMOS gates to a single equivalent transistor is introduced. The width of the equivalent transistor is calculated taking into account the operating conditions of each transistor in the structure, resulting in very good agreement with SPICE simulations. Second order effects such as carrier velocity saturation in submicron devices, body effect and co...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

Pass transistor logic is a promising alternative to conventional CMOS logic for low-power high-performance applications due to the decreased node capacitance and reduced transistor count it offers. However, the lack of supporting design automation tools has hindered the widespread application of pass transistors. In this paper, a simple and robust modeling technique for the timing analysis of t...

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely lo...