The tip-clearance flow in axial turbomachines is studied using large-eddy simulation with particular emphasis on understanding the underlying mechanisms for viscous losses in the end-wall region and the unsteady characteristics of the tipleakage vortical structures. Systematic and detailed analysis of the mean flow field and turbulence statistics has been made in a linear cascade with a moving ...

In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric...

Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce...

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full ad...

An active leakage-injection scheme (ALIS) for lowvoltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a commondrain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages ...

This paper presents a modified z-source inverter which is an effective method for reduction of leakage current in three phase transformer less grid connected PV systems. Another modulation technique along with z-source used are space vector pulse width modulation technique which improves the accuracy of leakage current by maintaining common mode voltage (CMV) constant. The new topology only req...

Today trend is circuit characterized by reliability, low power dissipation, low leakage current, low cost and there is required to reduce each of these. To reduce device size and increasing chip density have increase the design complexity. The memories have provided the system designer with components of considerable capability and extensive application. Dynamic random access memory (DRAM) give...

The continuous scaling down of technology, there is the exponential increase in leakage current. The MTCMOS is an attractive design to reduce the leakage current in idle state. Sleep-to-Active mode transition is an important concern in MTCMOS circuit because it produces ground bounce noise. In this paper, Threshold Voltage tuning method with MTCMOS circuit is used to reduce the ground bounce no...

In this paper the gate leakage current analysis of the Conventional 6T SRAM, NC-SRAM, PP SRAM, and P3 SRAM cell has been carried out. It has been observed that due to pMOS stacking and direct supply body biasing in the P3 SRAM Cell, there is a reduction of gate leakage current 66.55%, 34.42%, and 90.99% with respect to the 6T, NC-Cell, and PP cell, respectively for VDD=0.8V. For VDD=0.7V, it is...

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phaselocked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced ...