The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; t...

--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detec...

This paper focuses on the modeling and analysis of phase-locked loops in the presence of continuous wave (CW) interference such that the operating vulnerability to CW jamming and interference can be accessed. The loop phase error is characterized, and the conditions under which the loop remains locked in frequency to the desired carrier are presented. Analysis is conducted for arbitrary offsets...

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power effic...

We investigate the end of the inflationary period in the recently proposed scenario of locked inflation, and consider various constraints arising from density perturbations, loop corrections, parametric resonance and defect formation. We show that in a scenario where there is one long period of locked inflation, it is not possible to satisfy all of these constraints without having a period of s...

— We present a new technique for blind equalization of multiple-input multiple-output (MIMO) communication channels. In scalar channels it is common to follow a blind equalizer adapted according to the constant-modulus algorithm (CMA) by a phase-locked loop to compensate for carrier frequency offset. We generalize this structure to multiple dimensions , and propose to follow a blind MIMO equali...

Frequency countings close to a phase locked zone in an electronic receiver show a 1/f power spectral density. The noise scaling versus the frequency deviation and the open loop gain is found from Adler’s model of the phase locked loop. This fully agrees with experiments performed at 5 MHz on a receiver with a Schottky diode mixer and a low pass filter. The 1/f amplitude and frequency noise due ...

There is several application of phase locked loop in the field of communication. It depends on the mixed signal operation. It is capable of fast locking capability. present work based on redesign of the PLL system using 90nm technology process at frequency 1 GHz and the lock time is 179.5 ns and transient analysis of the PLL is simulate between 1ns to 1000ns.it consumes the 179.5 mW power at 1....

An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) [1] is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptiv...

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2...