This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect...

The nonlinear distortion of frequency or phase modulation systems composed by a voltage-controlled oscillator (VCO) modulator and a phase-locked loop (PLL) discriminator is addressed. Volterra series nonlinear transfer functions up to third order, for an LC Colpitts type modulator and a PLL with simultaneous nonlinear phase-detector and VCO, are combined as a cascade of mildly nonlinear systems...

Phase-locked loops (PLL) have found applications in many industrial applications such as communication and control systems. The key requirements are stability and loop performance in terms of signal-to-noise ratio and tracking errors. Here we present a two-step approach to PLL design. First, we present a Lyapunov approach to analyze the loop stability. The parameter range that can guarantee sta...

Noise performance of a phase-locked loop (PLL) based frequency modulation Kelvin force microscope (FM-KFM) is assessed. Noise propagation is modeled step by step throughout the setup using both exact closed loop noise gains and an approximation known as "noise gain" from operational amplifier (OpAmp) design that offers the advantage of decoupling the noise performance study from considerations ...

In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the perform...

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has b...

To acquire images of dynamic scenes from multiple points of view simultaneously, the acquisition time of vision sensors should be synchronized. This paper describes an illumination-based synchronization method derived from the phase-locked loop (PLL) algorithm. Incident light to a vision sensor from an intensity-modulated illumination source serves as the reference signal for synchronization. A...

A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS pr...

As the weak link in global navigation satellite system (GNSS) signal processing, the phase-locked loop (PLL) is easily influenced with frequent cycle slips and loss of lock as a result of higher vehicle dynamics and lower signal-to-noise ratios. With inertial navigation system (INS) aid, PLLs' tracking performance can be improved. However, for harsh environments with high dynamics and signal at...

In a phase-locked loop (PLL), it is critical to understand how reference clock noise affects the output quality, particularly in applications where PLLs are cascaded. That is, where the output of one PLL serves as the reference clock for another PLL. Traditionally, this problem is solved by qualitative analyses, rules of thumb, and simulation, all of which require confirmation with measurements...