This paper presents effective design of ternary ALU using Carbon Nano tube Field effect transistor (CNTFET) atv32 nm technology. Ternary logic is possible substitutes to traditional binary logic, because more number operation can performed using ternary logic as compare to binary logic due to this possible to achieve simplicity and energy efficient inrecent digital logic design due to reduced c...

Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In sequential precomputation, output values required in a particular clock cycle are selectively precomputed one clock cycle earlier, and the original logic circuit is “turned...

The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses....

of the Thesis Energy-Performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits by Fengbo Ren Master of Science in Electrical Engineering University of California, Los Angeles, 2011 Professor Dejan Marković, Chair Magnetic Tunnel Junction (MTJ) devices are CMOS compatible with high stability, high reliability and non-volatility. All these features are promising fo...

The goal of blif is to d escribe a logic-level hierarchical circuit in textual form. A circuit is an arbitrary combinational or sequential network of logic functions. A circuit can be viewed as a directed graph of combinational logic nodes and sequential logic elements. Each n o d e h as a two-level, single-output logic function associated with it. Each feedback l o o p m ust contain at least o...

This paper presents a performance analysis of hybrid 1-bit full-adder circuit design. The adder cell is dissected into smaller modules. The modules are analyzed and calculated extensively. To explore good-drivability, noise-robustness, and low-energy operations for deep sub micrometer to explore hybrid-CMOS style design. Hybrid-CMOS design style uses various CMOS logic style circuits to constru...

In-circuit testers are widely used for manufacturing tests and for the measurement of printed circuit board (PCB) systems. In-circuit testers can also program and verify programmable logic devices (PLDs) that support in-system programmability (ISP). Using in-circuit testers to program ISP-capable devices allows device programming to fit into the standard manufacturing flow, reducing time-to-mar...

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effect Transistor (FET) dimensions enabled the semiconductor industry to fabricate digital systems with higher circuit density at reduced costs. T...