Abstract:Gating of the clock signal in VLSI chips is nowadays a mainstream methodology for reducing switching power consumption.several techniques to reduce dynamic power of which clock gating is predominant.clock gating is employed at all levels:system architecture,block design,logic design and gates.three gating methods are known.the most popular is synthesis based on the logic of underlying ...

Pass-Transistor Mapper (PTM), a logic synthesis tool speci cally designed for passtransistor based logic library that has only three basic cells, is reported. It exploits the close relationship between BDD representation of logic and the structure of pass-transistor logic cells to ensure e cient technology mapping. BDD variable order optimization is achieved through a genetic algorithm with dyn...

| Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the non-inverting nature of the logic and the complex timing relationships associated with the clock scheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitionin...

In this paper, an analysis is presented, which demonstrates the effect pre-logic factoring could have on an automated combinational logic synthesis process succeeding it. The impact of pre-logic factoring for some arbitrary combinatorial circuits synthesized within a FPGA based logic design environment has been analyzed previously. This paper explores a similar effect, but with the non-regenera...

Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances stud...

In this paper, we present a partitioning approach of parallel logic synthesis, which is diierent from the previous approaches which involved parallelization of individual operations within the synthesis algorithm. We partition the given logic circuits and distribute the partitions to diierent processors for synthesis. For good load balancing, partitioning algorithm is tuned so that the estimate...

We present the tool ANZU. ANZU takes a formal specification of a design and generates a functionally correct system if one exists. The specification is given as a set of linear temporal logic (LTL) formulas belonging to the class of generalized reactivity of rank 1. Such formulas cover the majority of the formulas used in practice. ANZU is an implementation of the symbolic reactive(1) approach ...

The ternary Quantum-dot Cellular Automata (tQCA) were demonstrated to be a possible candidate for the implementation of a future multi-valued processing platform. Recent papers show that the application of the adiabatic pipelining can be used to solve the issues of the tQCA logic primitives. The architectures of the resulting tQCAs become similar to their binary counterparts and the physical de...