Due to continuous advancements in modern technology processes which have resulted in integrated circuits with smaller feature sizes and higher complexity, current system-on-chip designs consist of many different components such as memories, interfaces and microprocessors. To handle this growing number of components, an efficient communication structure must be provided and incorporated during s...

Chip MultiProcessors (CMPs) have become the primary method of build high-performance microprocessors. Besides speed, major elements such as processing elements and network on chip, allocation and management of on-chip processors are also important factor to achieve high efficiency of future CMPs. In this paper, the authors study a Processor Allocator (PA), especially the issue of its memory uti...

Despite the move toward chip multiprocessing in the mid-2000s, the problem of machine energy consumption is still a prevalent and growing problem within the computing sector. To evaluate energy consumption at the application level, researchers were previously limited to specialized external instrumentation, modeling or simulation. Thankfully, new microprocessor designs have now exposed a handfu...

High Performance Computing architectures are expected to change dramatically in the next decade as power and cooling constraints limit increases in microprocessor clock speeds. Consequently computer companies are dramatically increasing on-chip parallelism to improve performance. The traditional doubling of clock speeds every 18-24 months is being replaced by a doubling of cores or other parall...

Increased power density, hot-spots, and temperature gradients are severe limiting factors for today’s state-of-the-art microprocessors. However, the flexibility offered by the multiple cores in future Chip Multiprocessors (CMPs) results in a great opportunity for controlling the chip thermal characteristics. When a process is to be assigned to a core, a thermal-aware scheduling policy may be in...

Chip Multiprocessors (CMPs) or multicore processors have paved the way for high performance microprocessor architectures. For most applications the CMP outperforms the superscalar architecture by a large margin in terms of performance per unit of power as well as throughput. A lot have to be explored in terms of its implementation to exploiting its numerous possibilities of ever increasing perf...

The paper proposes an algorithm to calculate the switching angles using harmonic elimination PWM (HEPWM) scheme for voltage source inverter. The algorithm is based on curve fittings of a certain polynomials functions. The resulting equations require only the addition and multiplication processes; therefore, it can be implemented efficiently on a microprocessor. An extensive angle error analysis...

Long a proponent of simple, fast processors, HP has succumbed to the siren call of complexity, creating the most feature-filled RISC design yet revealed. Steve Manglesdorf, presenting at last month’s Microprocessor Forum, said that the forthcoming PA-8000 will achieve high clock rates despite the burden of this feature set, a powerful combination that he claims will create the industry’s fastes...

The rapid progress in high-performance microprocessor design has made it diicult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an unfortunate gap between real-time scheduling theory and its practice. In light of current and expected trends in commercial microprocessor architecture design, it is therefore important to make a qualitative assessment o...

A self-checkpointing microprocessor periodically copies the state of the currently-executing program to on-chip non-volatile storage, allowing it to resume execution of the program at the last checkpoint after a power supply interruption or shutdown. In this paper, we present a register file cell for a selfcheckpointing microprocessor, which integrates a magnetoelectronic non-volatile memory ce...