 This paper presents an application of an adapted (R-L-M-C) PEEC method dedicated to the extraction of equivalent circuit of power electronics devices. Two dedicated integral methods with different meshes are used to compute either resistive and inductive elements or capacitive couplings. The adaptive multi-level fast multipole method (AMLFMM) is presented to extract parasitic capacitances on ...

In this paper, we propose an analytical model to compute parasitic coupling capacitance between interconnects on different layers and substrate capacitance. In this method, electric flux is geometrically approximated to model the different capacitive components which combine to determine the overall equivalent capacitance. Based on our approach, capacitances of typical interconnect geometries c...

This paper examines the possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of 64 256 sensing cells (chip size: 2.7 10.8 mm2). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic capacitances. Thus, the reduced sensing-capacitor size enables a high resolution of 600 dpi, even using a conventional ...

An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simpl...

Introduction The low-band-gap, high mobility InAs semiconductor is well suited for nanowire devices. So far, fascinating DC characteristics of InAs nanowire field-effect transistors (NW-FETs) [1],[2] have been shown, whereas the high speed potential is not yet demonstrated. The major challenges towards a reliable RF characterization of single nanowire transistors, regardless of the material sys...

ABSTRACT The important practical and realistic design issues of an electrostatic actuator/positioner with full-gap travel are discussed. Analytic expressions and numerical simulations show that parasitic capacitances, and non-uniform deformation in two and three dimensions influence the range of travel of an electrostatic positioner stabilized by the addition of a series capacitor. The effects ...

A new technique for bandwidth enhancement of amplifiers is developed. Adding several passive networks, which can be designed independently, enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known filter component values...

A few years ago, Fairchild Semiconductor introduced the BGA as the power package of the future. The BGA package offers superior parasitic resistance and inductance compared to all of the traditional power packages like DPAK, D2PAK, etc. The SO8 package has been the package of choice for the notebook computing market for a very long time. Most design engineers feel comfortable designing SO8 MOSF...

Nanoscale CMOS Modeling by Mohan Vamsi Dunga Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Ali M. Niknejad, Chair Since its inception almost four decades ago, the conventional planar bulk silicon MOSFET has been scaled relentlessly in accordance with the Moore’s Law. However, as the state-of-the-art MOSFET makes inr...

A TSPC full-adder circuit containing only 6 clock transistors and thus consuming signi cantly less power than recently published full-adders has been designed and characterized by simulation. It is composed of 36 transistors and consumes 220 W @100 MHz when connected to a 5 V power supply, using a 0.8 m standard CMOS process technology. This considers all parasitic capacitances as well as the p...