Abstract: A Wallace tree multiplier using modified booth algorithm is proposed in this paper. It is an improved version of tree based Wallace tree multiplier [1] architecture. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of booth algorithm, 5:2, 4:2, and 3:2 compressor adders. An efficient VerilogHDL cod...

We show that a number of well known multiplier theorems for Hardy spaces over Vilenkin groups follow immediately from a general condition on the kernel of the multiplier operator. In the compact case, this result shows that the multiplier theorems of Kitada [6], Tateoka [13], Daly-Phillips [2], and Simon [11] are best viewed as providing conditions on the partial sums of the Fourier-Vilenkin se...

Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at the filter taps effe...

ABSTRACT : A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented ...

Let G be any group and let K(G) denote the multiplier Hopf algebra of complex functions with finite support in G. The product in K(G) is pointwise. The comultiplication on K(G) is defined with values in the multiplier algebra M(K(G)⊗K(G)) by the formula (∆(f))(p, q) = f(pq) for all f ∈ K(G) and p, q ∈ G. In this paper we consider multiplier Hopf algebras B (over C) such that there is an embeddi...

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier design is the 53x53 multiplication of the mantissas (52 bit mantissa+1 hidden bit). This paper proposes a approach to improve this performance bottleneck by adding a redundant 54 bit initialized to ‘0’ in the mantissas o...

Let X,Y be locally convex spaces and L(X,Y ) the space of continuous linear operators from X into Y . We consider 2 types of multiplier convergent theorems for a series P Tk in L(X,Y ). First, if λ is a scalar sequence space, we say that the series P Tk is λ multiplier convergent for a locally convex topology τ on L(X,Y ) if the series P tkTk is τ convergent for every t = {tk} ∈ λ. We establish...

The use of regression-based specification tests, such as the nR2 form of the Lagrange Multiplier test, has become quite widespread over the last 20 years. The popularization of the nR2 form of the Lagrange Multiplier (LM) test, perhaps the most widely used class of regression-based tests, has come about in large part from the ease of its application to many tests of nonlinear restrictions and i...

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop ...

In this paper Modified Booth Multiplier (radix-4) implemented by various adder. Partial product generated by booth encoder is added by various adder techniques to compare the performance parameter of multiplier. Performance parameter like area, path delay, fan out, speed of multiplier. Multiplication is an important fundamental function in arithmetic logic operation. Since, multiplication domin...