A memory design based on logi cal banks is analyzed for shared memory mul tiprocessor systems In this design each phys ical bank is replaced by a logical bank consist ing of a fast register and subbanks of slower memory The subbanks are bu ered by in put and output queues which substantially re duce the e ective cycle time when the refer ence rate is below saturation The principal contribution ...

In this paper we present a multiprocessor semantics for CCS [Mil80]. An operational semantics for processes under a nite number of processors is developed. The e ect of adding or removing processors from the system is studied. A notion of strong bisimulation induced by the new semantics is de ned. Issues related to a complete axiomatization of this congruence are examined and a complete equatio...

In simulation–based performance evaluation, the simulation time is directly related to the complexity of the simulated systems. Since modern multiprocessor systems contain hundreds and even thousands of processors, simulation of such systems can be quite time–demanding. This paper studies multiprocessor systems with different numbers of processors but with the same utilizations of corresponding...

In larger development projects, DSP programming groups often operate in a separate silo from the GPP and FPGA programmers. This is a problem because the groups must coordinate their efforts in order to design an optimal system architecture and to allocate functionality optimally. This coordination can be time-consuming and challenging. What's more, any changes to the system architecture or func...

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP’s, ASICS, and FPGA subsystems. Thus, it is particularly well-suited to the ev...

This paper presents a methodology and techniques for automated integration of dedicated hardwired (HW) IP cores into heterogeneous multiprocessor systems. We propose an IP core integration approach based on an HW module generation that consists of a wrapper around a predefined IP core. This approach has been implemented in a tool called ESPAM for automated multiprocessor system design, programm...

We consider the problem of scheduling of n independent jobs on m unrelated machines to minimize the max(t1, t2, ..., tm), ti being the completion time of machine i. In [1] was suggested a polynomial 2approximation algorithm for this problem. It was also proved that there can exist no polynomial 1.5-approximation algorithm unless P = NP . Here we improve this earlier performance bound 2 to 2− 1 ...

The model is inspired from [2] (see also [1, 3]). Consider a multiprocessor system with a shared memory. Processes running on this system have to compete for access to the common memory: to gain access and to use the common memory they need also to acquire the system bus which is released when access to the common memory is terminated; for simplicity the bus will not be explicitly represented i...

This paper presents a general theory for modeling and designing fault-tolerant multiprocessor systems in a systematic and efficient manner. We are concerned here with structural fault tolerance, defined as the ability to reconfigure around faults in order to preserve the interconnection structure of a multiprocessor. We represent multiprocessor systems by graphs whose node sets denote processor...

This work proposes a hardware-software partitioning approach named GHO to solve the partitioning issue for embedded multiprocessor FPGA systems. GHO adopts genetic algorithm and hardware-oriented partition to improve the partitioning result with faster execution time, smaller memory size and higher slice usage under satisfied system constraints. Two experimental results demonstrate that GHO is ...