This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC to...

Nowadays design paradigms of highly complex and integrated Systems-on-a-Chip (SoC) are based on the assembling of predesigned cores and components (Intellectual Property, IP cores). That way, test and development cycles —and finally the time-to-market— can be reduced. To have the manyfold components interoperate with each other in order to get the desired functionality, interconnections between...

General purpose routing algorithms for a network-on-chip (NoC) platform may not be able to provide sufficient performance for some communication intensive applications. This may be because of low adaptivity offered by a general purpose routing algorithm resulting in some links getting highly congested. In this study the authors demonstrate that it is possible to design highly efficient applicat...

The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-dimensional integration (3D), as well as network-on-chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for powerefficient application mappin...

Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability. The chip scenario has the particularity that is static, and the multipath can be known a priori. Within this context, we propose in this paper ...

Network-on-Chip (NoC) has been introduced to meet the communication challenges for on chip multi-processors and the bandwidth of NoC takes a significant role in area and power consumption of overall system. In order to minimize the bandwidth requirement of NoC, a mapping method is proposed to schedule the tasks of an application onto NoC architecture. More precisely, given the application task ...

To address the ever increasing bandwidth requirements of next-generation high-performance systems, FPGA vendors are continually making incremental improvements in their device architectures. Even with these advanced architectures, designers often resort to implementing their designs using very wide on-chip buses. In fact, on-chip buses of 512, 1,024 or 2,048 bits wide are increasingly common. A...

While higher chip rate can provide better performance for Direct Sequence/Code Division Multiple Access (DS/CDMA) systems due to larger process gain, it may also induce spectrum emission to adjacent channels, i.e., adjacent channel interference. Especially, if different operators use adjacent channels in the same area with uncoordinated power levels, such interference becomes large, and excessi...

Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer’s peak temperature and traffic to prolong chip’s service life. In this paper, we propose a heat-balanced, deadlock-free routing algorithm named Direct Ratio Transport Layer (DRTL). DRTL distributes and arranges traffics according to the ...

A generic analytical performance model of singlechannel wormhole routers is presented using the M/D/1/B queuing theory. Compared with previous work, the flowcontrol feedback mechanism is studied in detail, and a computing method bases on Markov chain for the flowcontrol feedback probability is proposed. Compared with BookSim, a well-known cycle-accurate Network-on-Chip (NoC) simulator, this mod...