نتایج جستجو برای: pipelining
تعداد نتایج: 1926 فیلتر نتایج به سال:
High-performance processors will increasingly rely on multibanked first-level caches to meet frequency requirements. In this paper we introduce replication degree and data distribution as the main multibanking design axes. We sample this design space by selecting current data distribution policy proposals, measuring them on a detailed model of a deep pipelined processor and evaluating the trade...
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contributor to these uncertain latencies is the use of cache memories required to provide adequate memory access speed in modern processors. Scheduling for instruction-level parallel architectures with nonblocking caches usua...
Recent advances in cluster le systems, network memory, and network-attached disks make it possible to construct storage systems whose performance tracks network technology rather than disk technology. However, delivering the potential of high-speed networks for network storage systems depends on communication support that meets client demands for low network latency for random block accesses an...
A new structure is presented for digital delta-sigma modulator (DDSM). Novel architecture decreases hardware consumption, output quantization noise and spurs in Comparison to previous architectures. In order to reduce the delay, power consumption and increase maximum working frequency, the pipelining technique and the carry skip adder are used. Simulation proposed architecture shows that the qu...
The growth in size and complexity of convolutional neural networks (CNNs) is forcing the partitioning a network across multiple accelerators during training pipelining backpropagation computations over these accelerators. Pipelining results use stale weights. Existing approaches to pipelined avoid or limit weights with techniques that either underutilize increase memory footprint. This paper co...
Decoupled software pipelining [5] presents an easy way to automatically extract thread-level parallelism for general loops in any program. The compiler does this by examining the dependences of the loops in a given program, splitting the instructions of those loops into multiple smaller loops that execute in independent threads, and inserting dependence communication where necessary between the...
This paper presents an approach to software pipelining of nested loops. While several papers have addressed software pipelining of inner loops, little work has been done in the area of extending it to nested loops. This paper solves the problem of nding the minimum iteration initiation interval (in the absence of resource constraints) for each level of a nested loop. The problem is formulated a...
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