This paper presents a novel current mode four quadrant multiplier. A pair of sub threshold translinear loops and current conveyors are the basic building blocks in realization scheme. The proposed multiplier features simplicity, low power dissipation. The salient features of this approach are; it‟s single ended inputs; since it uses sub threshold region of operation, this make the design intere...

In the framework of the stochastic dynamics of open Markov systems, we derive an extension of the Clausius inequality for transitions between states of the system. We give a formula for the power produced when the system is in its stationary state and relate it to the dissipation of energy needed to maintain the system out of equilibrium. We deduce that, near equilibrium, maximal power producti...

A computational complexity, power consumption, and receiver sensitivity analysis for three different scenarios for short-range direct detection links is presented: 1) quad-polarization, 2) wavelength division multiplexing (WDM), and 3) parallel optics. Results show that the power consumption penalty associated to the quad-polarization digital signal processing (DSP) is negligibly small. However...

An MOS ternary-logic family is proposed, which is comprised of a set of inverters, NOR gates, and NAND gates. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other kno...

In this article, a new approach for the efficient design of quantum-dot cellular automata (QCA) circuits is introduced. The main advantages of the proposed idea are the reduced number of QCA cells as well as increased speed, reduced power dissipation and improved cell area. In many cases, one needs to double the effect of a particular inter median signal. State-of-the-art designs utilize a kind...

A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

The Gate diffusion input (GDI) is a novel technique for low power digital circuit design. This technique reduces the power dissipation, propagation delay, area of digital circuits and it maintains low complexity of logic design. In this paper, the 4×1 Multiplexer, 8×3 Encoder, BCD Counter and Mealy State Machine were implemented by using Pass Transistors (PT), Transmission Gate (TG) and Gate Di...

For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to BuiltIn Self Test (BIST) can represent a significant percentage of the overall power dissipation. One possible solution to address this problem consists of test pattern reordering with the purpose of reducing the amount of pow...

A method to reduce the power dissipation of analog-todigital converters (ADCs) in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this paper, we present an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-...