Abstract—This paper introduces two new type active quasi circulators and three new type active circulators which use the outof-phase power divider/combiner, symmetric/anti-symmetric couplers and generic unilateral amplifiers. The proposed circuits are full-symmetric and composed of conventional microwave devices. Analytical relations for active quasi circulator modules are described. These modu...

In this paper we are presenting novel current multiplier/divider circuits utilizing the power of FGUVMOS transistors. Even for ultra low supply voltages a proper operation is achieved with threshold shifting using post-fab. tuning. Measured results are provided of a multiplier working over a large magnitude in current at 0.7V power supply.

This paper discussed the circuit level design and simulation of fractional-N frequency divider, a circuit block used mainly in frequency synthesizer. The design was done in schematic level. A low power 0.5 micron CMOS technology called CMOSIS5 used for modeling the circuit devices. The frequency divider was design for 900 MHz GSM standard mobile communication application. For the simulation, ci...

In this note we examine the change of the PMT pulse gain as a function of DC background current using an active divider and compare its behavior to the one obtained using a passive network. We show that the present version of the active divider results in: 1) constant gain over a large background current (rendering possible to operate the FD under the presence of some backscattered moon light, ...

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 m CMOS technology. Configured as a master-slave circuit, the ...

This article details the design of six-port direct conversion front-end module for dual-band (1.575GHz and 2.680GHz) applications. Proposed planar architecture consists of single-stage (1:2) Wilkinson Power Divider and three numbers of quarter-wave 3-dB branch-line couplers working simultaneously at dual band of frequencies. Present article describes the designing of each building block and fin...

Manuscript Received 26-February-2013 and revised 23-June-2013 ISSN 2322-3936 Accepted on 2July-2013 Abstract— This paper proposes a two way L and S band Gysel power divider/combiner that uses line to ground resistors. Step by step methods to obtain a wide isolation and transmission bandwidth are presented. A design that uses five resistors is selected and optimized based on Quasi Newton method....

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a resul...