نتایج جستجو برای: qca full adder

تعداد نتایج: 299779  

2011
GEETHA PRIYA

Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power VLSI design. This paper proposes a new reversible parallel adder/subtractor using 4*4 Reversible DKG gate that can work singly as a reversible full adder and a full subtractor. A serial adder/subtractor is also designed in this paper using Reversible Universal Shift registers and DK...

2016
A. Roohi H. Thapliyal R. F. DeMara

Quantum-dot Cellular Automata (QCA) seek potential benefits over CMOS devices such as low power consumption, small dimensions, and high speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three-step Bilayer Logic Decomposition (BLD) methodology to design QCA-based logic circuits. The partitioning of QCA computing operation...

Journal: :Microelectronics Reliability 2014
Muhammad Ali Akbar Jeong-A Lee

Keywords: Self-checking adder Carry-select adder Fault localization Self-repairing adder Multiple faults a b s t r a c t In this paper we propose an area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder. Fault detection and recovery has been carried out using self-checking full adders that can diagnose the fault based on internal funct...

2010
Basil George Nikhil Soni

Full adders are important components in applications such as digital signal processors (DSP) architectures and micro-processors. In this paper, we propose a technique to build a total of 3 low power 10 transistor full adder using x-nor gates. We have done around 10 simulation runs of each adder for different frequencies, load capacitance and input patterns. Almost all the new adders consume les...

2016
Sherpal Kaur Parminder Singh Neil H. E. Weste David Harris Ayan Banerjee Yusuf Leblebici Manoj Kumar Sandeep K. Arya Sujata Pandey Mohammad Hossein Moaiyeri Reza Faghih Mirzaee Keivan Navi Amin Bazzazi Alireza Mahini Yongtae Kim Yong Zhang Peng Li Deepa Sinha Tripti Sharma K. G. Sharma Jin-Fa Lin Yin-Tsung Hwang Ming-Hwa Sheu Cheng-Che Ho

In this paper, we designed and simulated a low power one bit, 8-bit and 32-bit full adder circuits namely Novel 10T, N14T, FA24T, CPL (complementary pass-transistor logic) and DPL (double pass-transistor logic). All the adders are tested by using one bit, 8-bit and 32-bit ripple carry adder architecture using Tanner EDA tool version 13. 0. The one bit Novel 10T, N14T, XOR/XNOR function techniqu...

2016
K. Mariya Priyadarshini M. Naga Sabari

Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is proposed with very less static and dynamic power dissipation which occupies less silicon area when compared with existing t...

2005
Valeriu Beiu Asbjørn Djupdal Snorre Aunet

In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power consumption applications. The elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. These simulations confirm that wires play...

2016
P. Balasubramanian S. Yamashita

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing as...

Journal: :IEICE Electronic Express 2015
Bosheng Liu Ying Wang Zhiqiang You Yinhe Han Xiaowei Li

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a stu...

In this paper, a Dual-Bit Parallel Adder (DBPA) based on minority function using Carbon-Nanotube Field-Effect Transistor (CNFET) is proposed. The possibility of having several threshold voltage (Vt) levels by CNFETs leading to wide use of them in designing of digital circuits. The main goal of designing proposed DBPA is to reduce critical path delay in adder circuits. The proposed design positi...

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