نتایج جستجو برای: reconfigurable instruction set processor

تعداد نتایج: 740389  

2015
Mohammad Javad Dousti Alireza Shafaei Massoud Pedram

We present a multi-core reconfigurable quantum processor architecture, called Requp, which supports a hierarchical approach to mapping a quantum algorithm while sharing physical and logical ancilla qubits. Each core is capable of performing any quantum instruction. Moreover, we introduce a scalable quantum mapper, called Squash 2, which divides a given quantum circuit into a number of quantum m...

Journal: :Quantum Information & Computation 2016
Mohammad Javad Dousti Alireza Shafaei Massoud Pedram

We present a multi-core reconfigurable quantum processor architecture, called Requp, which supports a hierarchical approach to mapping a quantum algorithm while sharing physical and logical ancilla qubits. Each core is capable of performing any quantum instruction. Moreover, we introduce a scalable quantum mapper, called Squash 2, which divides a given quantum circuit into a number of quantum m...

2008
Won-young Chung Yeo-phil Yoon Yong-surk Lee

In this paper, we propose a new instruction set for a network ASIP(Application Specific Instruction-set Processor). The new instruction set was designed for the packet processing engine on a network router. The network ASIP to accelerate the packet processing operation was built on a baseline ASIP, which is based on the general RISC structure. The new instruction set is divided into two groups....

2006
Mitsumasa Koyanagi Takeaki Sugimura Tetsu Tanaka

We have proposed a new reconfigurable parallel image processing system in which three-dimensional (3D) LSI is used. A new dynamical multi-context reconfiguration scheme is employed in this system. This scheme can decrease the number of instructions between a reconfigurable processing element array and control RISC processor, and also enable efficient execution of various image processing functi...

2009
Sandro Bartolini Roberto Giorgi Enrico Martinelli

Instruction-set extension (ISE) has been widely studied as a means to improve the performance of microprocessor devices running cryptographic applications. It consists, essentially, in endowing an existing processor with a set of additional instructions that can be useful for speeding-up specific cryptographic computations. Recently, researchers became aware of the following: ”The efficiency of...

2002
James E. Smith

Microprocessors are designed to provide good average performance over a variety of workloads. This can lead to inefficiencies both in power and performance for individual programs and during individual phases within the same program. Microarchitectures with multi-configuration units (e.g. caches, predictors, instruction windows) are able to adapt dynamically to program behavior and enable/disab...

2013
Sudeep Kanur Chandra Shekar Johan Lilius Sebastien Lafond

High quality digital video transmission requires efficient and reliable data communication over broadcasting channels as there is a risk of data corruption associated during transmission. The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its use in second generation Digital Video Broadcasting (DVB) standards for mobile, cable, satellite and terrestrial channels...

Journal: :IEEE Trans. VLSI Syst. 2001
Michael Gschwind Valentina Salapura Dietmar Maurer

Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain. In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and des...

1998
Jin-Hyuk Yang Byoung-Woon Kim Sang-Jun Nam Jang-Ho Cho Sung-Won Seo Chang-Ho Ryu Young-Su Kwon Dae-Hyun Lee Jong-Yeol Lee Jong-Sun Kim Hyun-Dhong Yoon Jae-Yeol Kim Kun-Moo Lee Chan-Soo Hwang In-Hyung Kim Jun-Sung Kim Kwang-Il Park Kyu-Ho Park Yong-Hoon Lee Seung-Ho Hwang In-Cheol Park Chong-Min Kyung

This paper describes the MetaCore system which is an ASIP(Application-Speci c Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to o er an e cient design methodology meeting speci cations given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and des...

1997
C. John Glossner Stamatis Vassiliadis

In this paper we introduce the Delft-Java multithreaded processor architecture and organization. The proposed architecture provides direct translation capability from the Java Virtual Machine instruction set into the Delft-Java instruction set. The instruction set is a 32-bit RISC instruction set architecture with support for multiple concurrent threads and Java speci c constructs. The parallel...

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