Fault Modeling, Delay Evaluation and Path Selection for Delay Test Under Process Variation in Nano-scale VLSI Circuits. (December 2005) Xiang Lu, B.S., Xi'an Jiaotong University; M.S., Xi'an Jiaotong University Chair of Advisory Committee: Dr. Weiping Shi Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this d...

This article analyzes the transient stability of an offshore wind farm connected via modular multilevel converter (MMC)-based high-voltage direct-current transmission system. The is composed by full-scale type-4 turbines, whereas short-circuit faults occurring in between MMC and are considered. tends to be switched current limiting mode or overmodulation during ac-side fault, which further inte...

Although the introduction of distributed generation (DG) in a distribution system improves the power quality of power system, it increases the fault current level reducing voltage at point of common-coupling (PCC). Hence, there is a need of improving fault ride-through (FRT) capability to avoid sudden tripping of DG units from the utility grid during voltage sag in a faulty condition. In this p...

This paper proposes a fuzzy logic controller (FLC) based variable resistive bridge type fault current limiter (VR-BFCL) to minimize the impact of faults on voltage source converter high direct (VSC-HVDC) systems. FLC for VR-BFCL is developed dynamically insert appropriate limiting resistance during contingencies maintain currents within acceptable limit. The proposed effectively provides duties...

This paper introduces the indicators for surge arrester condition assessment based on the leakage current analysis. Maximum amplitude of fundamental harmonic of the resistive leakage current, maximum amplitude of third harmonic of the resistive leakage current and maximum amplitude of fundamental harmonic of the capacitive leakage current were used as indicators for surge arrester condition mon...