This paper describes a 60-GHz differential power amplifier (PA) designed in a 120-GHz fT 90nm CMOS technology. It consists of three identical differential cascode stages with inter-stage matching implemented by wide-gap coplanar waveguide (CPW) structures and M6M5 plate capacitors. A double-stub network realized by CPWs provides more design freedom for the input matching. Load-pull simulation g...

* D Abstract --Lossless broad-band microwave active inductors for generalpurpose use in microwave circuits are proposed and their characteristics are discussed. These active inductors are composed of a common-source cascode FET and a feedback FET, and operate in a wide frequency range with very low series resistance. A maximum Q factor of 65 is obtained. Theoretically, it can reach infinity. Fu...

This work presents a study of the use of a transistor with a different configuration in the channel region, named GradedChannel (GC), for analog application in current mirror circuits with different architectures: Common-source, Cascode and Wilson. A comparison will be done between current mirrors implemented with standard (uniformly doped) SOI and GC SOI nMOSFETs by using simulation and experi...

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35 um standard CMOS technology. The DC gain achieved is 56.7...

In this paper, a formal design approach for the differential cascode voltage switch with pass gate (DCVSPG) logic is presented. This permits the design of any combinational logic function by the use of a k-map or by a modified QuineMcCluskey algorithm. The basic design approach used is based on pass logic and shows that a DCVSPG logic gate designed with minimum number of transistors may not alw...

In this paper we propose a design path for optimization-based device sizing of analog circuits. The design path offers an efficient and reliable way to implement high-performance analog integrated circuits without the explicit knowledge of an experienced designer. A key feature is that the partial cost functions are generated directly from the circuit topology. To demonstrate the functionality ...