This paper presents a nano-watt bandgap voltage reference (BGR). The self-cascode structure is provided as proportional-to-absolute-temperature (PTAT) voltage. Due to the low slope of PTAT voltage, divider consisting five similar MOSFET transistors presented. resulting output will be one-fifth complementary-to-absolute-temperature and four-fifths All MOSFETs are standard CMOS biased in sub-thre...

The design of a fully differential CMOS transconductance amplifier is presented in this paper. This amplifier is to be used in the first stage of a 13-bit pipelined A/D converter, and was designed to meet the necessary specifications at a minimum level of power consumption. The amplifier presented below was based on a two-stage design of a telescopic cascode input stage followed by a common-sou...

In order to achieve an overall noise of less than 1000 electrons per channel for a typical input capacitance of a total of 5-10 pF, the use of a low-noise circuit is required. A well proven topology to fulfil such a requirement is shown in fig. 1. Each channel consist of a low noise chargesensitive amplifier, an active CR-(RC) pulse shaper. The main noise contributor is the input transistor of ...

The improvement of a conventional Gyrator-C active inductor consisting of common-emitter configured and common-collector configured with resistance feedback is presented. The fixed passive resistor is replaced with tunable active resistor (TAR) to enhance the adjustability of the active inductor. Multi-regulated Cascode (MRC) circuit is applied to boost quality factor Q. Compared with the conve...

This open-loop gain enhancement circuit in 1.2pm CMOS does not require cascode or long-channel transistors, thus maximizing output swing and input common-mode range [1,21. Since gain enhancement is achieved not by increasing output resistance, but by matching main and replica amplifiers, high effective open-loop gain is maintained even with resistive loads. This circuit can be used with any tra...

A circuit technique to correct Vdd/PM distortion and improve efficiency as supply modulation of cascode class-E PAs has been proposed. The experimental result shows that the phase distortion can be improved from 20 degrees to 5 degrees. Moreover, a system co-simulation result demonstrated that the EVM can be improved from −17 dB to −19 dB. key words: envelope elimination and restoration (EER), ...

of photodiode and transimpedance amplifier on a 12.4 Moisture Sensitivity and Soldering. narrowly-focused beam falling only on the photodiode provides improved settling times from allanalog circuits to data conversion base circuits. Q1 and Q2 form a "cascode" amplifier circuit. To compensate for the high-frequency rolloff of the photodiode, U1B is configured as Daylight modifications will drama...

Superharmonic injection locking is investigated in a new theoretical approach. Low power frequency dividers are designed using injection locked oscillators with cascode transistors. The Rockwell 0:5 m CMOS process is used to design a 3mW injection locked frequency divider in the 1800MHz frequency range. A 200MHz maximum locking range is achieved in simulations. 2SC3302 TOSHIBA NPN transistors a...

The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

The LNA is implemented using 90nm CMOS technology. The cascode topology with single-ended source degeneration using inductor is employed. The high gain is achieved by using common-source (CS) amplifier. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA. An inductance network (Lg, Ls) is used for input matching. An interstage ...