We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different approaches for this purpose: (1) Identical state encoding of the two sequential logic implementations, duplication of flip-flops, diverse implementation of the combinational logic part (output logic and next-state logic) and comparators on flip-...

This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing wit...

Power optimization is one of the important challenges in VLSI circuit for testing engineers. Larger power dissipation becomes the reason for overheating and with every increase in 10oC in operating temperature, failure rates for the component on a chip doubles. Power dissipation is directly proportional to switching activities of the components on Integrated Circuits. Power optimization is poss...

A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential...

ÐWe propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorte...

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous ...

Methods for Reducing Events in Sequential Circuit Fault Simulation Elizabeth M. Rudnick Thomas M. Niermann Janak H. Patel Center for Reliable and Sunrise Test Systems Inc. Center for Reliable and High-Performance Computing Sunnyvale, CA 94086 High-Performance Computing University of Illinois University of Illinois Urbana, IL 61801 Urbana, IL 61801 Abstract Methods are investigated for reducing ...

Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In this paper, we present new precomputation architectures for both combinational and sequential logic and describe new precomputation-based logic synthesis methods...

With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. All previous works on mapping sequential logic simulation algorithms onto general purpose parallel machines were centered around using Event-Dri...

Scan Based Delay Testing is used to perform delay testing in the sequential circuits which have the scan capability. In this paper, basics of delay testing and several techniques to perform delay testing for scan based circuits are discussed. The construction of several scan flip-flops along with their advantages and disadvantages is also presented.