Fig. 3 Logic Element (LE) of FP3 including the proposed TCM AbstractThis paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to reduce operation delay. Designed and fabricated in 0.35um 2P3M CMOS technology, F...

In this work, a new method to design a mixedmode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by Berlekamp–Massey algorithm (BMA) and is capable of generating pre-computed deterministic test patterns which detect the hard-to-detect faults of the circuit. Moreover, the LFSR generates residual patter...

With the development of various cryptographic primitives deployed on insecure devices, key exposure seems inevitable. Generalized from forward-secure signatures and key-insulated signatures, intrusion-resilient signatures (IRSs) was first introduced by Itkis and Reyzin, which help us to minimize the damage of key exposure. IRSs provide the unforgeability for the past and future time periods unl...

A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DSLFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is 1 th that of the normal clock, which drives the normal-speed ...

In this paper1, we present a new pseudo-random sequence generator, constructed by using two ternary linear feedback shift registers (LFSR). This new generator is called an editing generator which is a combined model of the clock-control generator (viewed as insertion) and the shrinking generator (viewed as deletion). It is shown that the editing generator has good properties of randomness, such...

This paper presents a new multiplication algorithm and, based on this algorithm, proposes a hardware architecture, called Modified Inner-Product Multiplier (MIPM), which computes AB multiplication based on a Linear Feedback Shift Register (LFSR). The algorithm is based on the property of the irreducible all one polynomial (AOP) over the finite field GF(2). The proposed architecture reduces the ...

This paper investigates the generation of a binary Modified Jacobi sequence by means of an additive combination of constituent binary Legendre sequences which are clocked at different rates. These multi-rate combinations demonstrate that sequences of large linear complexity can be generated without resorting to linear feedback shift registers (LFSRs) of large length. Results on the linear compl...

This short paper introduces the basic concepts of Stochastic Computing (SC), and presents additions to a remote lab with reconfigurable logic to allow testing SC circuits. Recently, SC has been revisited and evaluated as a possible way of performing approximate probabilistic computations for artificial perception systems. New modules allow the generation of pseudo-random numbers, given a seed k...

One way to create a random array is to map a random sequence into a two-dimensional pattern and an obvious choice is the use of shift-register sequences [10] or to use prime reciprocal sequences [11]-[14]. One dimensional binary random sequences are obtained as expansions of the prime reciprocal 1/p by [11],[12], a(i) = 2 mod p mod 2. Shift register (maximum length) sequences are obtained using...