The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

The LNA is implemented using 90nm CMOS technology. The cascode topology with single-ended source degeneration using inductor is employed. The high gain is achieved by using common-source (CS) amplifier. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA. An inductance network (Lg, Ls) is used for input matching. An interstage ...

This paper describes a 60-GHz differential power amplifier (PA) designed in a 120-GHz fT 90nm CMOS technology. It consists of three identical differential cascode stages with inter-stage matching implemented by wide-gap coplanar waveguide (CPW) structures and M6M5 plate capacitors. A double-stub network realized by CPWs provides more design freedom for the input matching. Load-pull simulation g...

* D Abstract --Lossless broad-band microwave active inductors for generalpurpose use in microwave circuits are proposed and their characteristics are discussed. These active inductors are composed of a common-source cascode FET and a feedback FET, and operate in a wide frequency range with very low series resistance. A maximum Q factor of 65 is obtained. Theoretically, it can reach infinity. Fu...

This work presents a study of the use of a transistor with a different configuration in the channel region, named GradedChannel (GC), for analog application in current mirror circuits with different architectures: Common-source, Cascode and Wilson. A comparison will be done between current mirrors implemented with standard (uniformly doped) SOI and GC SOI nMOSFETs by using simulation and experi...

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35 um standard CMOS technology. The DC gain achieved is 56.7...

In this paper, a formal design approach for the differential cascode voltage switch with pass gate (DCVSPG) logic is presented. This permits the design of any combinational logic function by the use of a k-map or by a modified QuineMcCluskey algorithm. The basic design approach used is based on pass logic and shows that a DCVSPG logic gate designed with minimum number of transistors may not alw...

In this paper we propose a design path for optimization-based device sizing of analog circuits. The design path offers an efficient and reliable way to implement high-performance analog integrated circuits without the explicit knowledge of an experienced designer. A key feature is that the partial cost functions are generated directly from the circuit topology. To demonstrate the functionality ...

Problem statement: The Low Noise Amplifier (LNA) is a core block of an Ultra Wide Band (UWB) receiver since it amplifies a very weak signal received at the antenna to acceptable levels while introducing less self-generated noise and distortions. The LNA design poses a unique challenge as it requires simultaneous optimization of various performance parameters like power gain, input matching, noi...

A modification of the conventional Flipped Voltage Follower (FVF) to enhance its output resistance is presented. It consists of replacing the conventional cascoding transistor of the basic cell by a regulated cascode scheme. This decreases the output resistance by a factor gmro approximately, the gain of a transistor as an amplifying stage. This is achieved with only two additional transistors ...