The use of high performance computers for wavelet and wavelet packet based image coding is discussed. After a short description of wavelet and wavelet packet methods the existing literature concerning vector, parallel and VLSI wavelet transforms is reviewed. In the following an algorithm for wavelet packet best basis selection on moderate parallel MIMD architectures is introduced and an impleme...

This paper presents a higher-order abstraction framework for process compositions which are common to highly-parallel systems and VLSI architectures. It is to aid reuse and formal design of such compositions. We construct the framework on functional programming, since it has a facility for process modeling and higher-order abstraction. Our achievements include a basis for inheritance and aggreg...

This thesis describes the development and testing of a simple visual system fabricated using complementary metal-oxide-semiconductor (CMOS) very large scale integration (VLSI) technology. This visual system is composed of three subsystems. A silicon retina, fabricated on a single chip, trar~sduces light and performs signal processing in a manner similar to a simple vertebrate retina. A stereoco...

Free-space optical interconnects will soon be able to provide input/output bandwidths to a VLSI chip in excess of a terabit per second. The successful application of this technology to parallel distributed processing systems depends on the need for high-bandwidth interconnects and the ability of the architecture to sustain a stream of data at these bandwidths to the processing elements. We revi...

The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. Th...

The advantages of the wavelet transform over conventional transforms, such as the Fourier transform, are now well recognized. Because of its excellent locality in time-frequency domain, wavelet transform is remarkable and extensively used for signal analysis, compressing and denoising. Defining DWT by Mallat [1] provided possibility of its digitally hardware or software implementation. The disc...

In this paper, we develop a scalable VLSI architecture employing a two-channel quadrature mirror filter (QMF) lattice for the one-dimensional (1-D) discrete wavelet transform (DWT). We begin with the development of systematic scheduling, which determines the filtering instants of each resolution level, on the basis of a binary tree. Then input–output relation between lattices of the QMF bank is...

In this paper we introduce inputloutput (I/O) overhead . 1c, as a complexity measure for VLSI implementations of two-dimensional lattice computations of the type arising in the simulation of physical systems. We show by pebbling arguments that. 1c, = s2(n-') when there are n2 processing elements available. If the results are required to be observed at every generation, and no on-chip storage is...

Fig. 3 Total silicon area versus number of inputs (n), with number of fuzzy sets constant List of Symbols n Number of inputs p Number of fuzzy sets A f Device area for fuzzifier circuit A m Device area for multiplier circuit A tad Total active device area A ts Total silicon area A s Device area for a summer circuit A ic Device area of intersection block A ti Total area for interconnect λ scalea...

This paper presents high-performance encoder and decoder architectures for a class of Low Density Parity Check (LDPC) codes. The codes considered here are based on the Parallelly Concatenated Parity Check encoder structure. A major advantage of these codes is that the generator matrix and the parity check matrix are both sparse, which leads to efficient VLSI implementations for the encoder and ...