نتایج جستجو برای: voltage stability margin

تعداد نتایج: 433600  

Journal: :SSRN Electronic Journal 2018

2013
A. Cheraghi Valujerdi

In this paper, a novel method based on Hybrid Genetic Algorithm and Particle Swarm Optimization (HGAPSO) technique is proposed for solving Under Voltage Load Shedding (UVLS) problem. Load curtailment as ultimate control action is performed by under voltage load shedding scheme to guarantee power system voltage stability in contingency conditions. In addition, the proposed under voltage load she...

Journal: :Appl. Soft Comput. 2015
Belkacem Mahdad Kamel Srairi

This paper presents a new power system planning strategy which combines firefly algorithm (FFA) with pattern search algorithm (PS). The purpose is minimizing total fuel cost, total power loss and reducing total voltage deviation, with the objective of enhancing the loading margin stability and consequently the power system security. A new interactive and simple mechanism, inspired in brainstorm...

2002
Jiang-Qian Ying Li Xu Masayuki Kawamata

Abstract In this paper, first, the stability margin and stabilizability margin of multidimensional (nD) systems are considered. In particular, the concept of stabilizability margin is introduced for the first time and it is defined to be the largest stability margin that a closed-loop feedback system can reach by menas of any stabilizing compensator. The investigation of stabilizability margin ...

2016
Sushil Kumar

ENHANCEMENT OF POWER SYSTEM STABILITY BY SIMULTANEOUS AC-DC POWER TRANSMISSION Dr. Sushil Kumar Principal Pragati college of Engg. & Management,Raipur [email protected] Abstract It is difficult to load extra high voltage (EHV) ac lines to their thermal limits as a sufficient margin is kept against transient instability.This paper proposed a model in which it will be possible to load these ...

2007
Kunhyuk Kang Muhammad Ashraful Alam Kaushik Roy

One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, f...

2011
Manoj Kumar Rohit Kumar

SRAM cell read stability and write-ability are major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, we studied and comparedthe performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) andconventional 6T structure.SRAM cells have been simulated in SPICE with 0.35 μm technology. The techniques that provide th...

2006
J. De Maeyer P. Rombouts L. Weyten

In this paper we propose a way to design continuous time Σ∆ modulators. The method is based on the Nyquist stability criterion. Based on this criterion we propose to use the vector gain margin as a robust stability margin. Using this margin as a design criterion we design a robustly stable modulator. Finally, we also show how this margin can be used to evaluate the relative stability of a desig...

2016
Vita Pi-Ho Hu

Abstract The impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability of ultra-thin-body (UTB) GeOI 6T SRAM cell and performance of sense amplifier compared with the SOI counterparts are analyzed and discussed in this report. Worst case stress scenarios for read and write operations are analyzed. For UTB GeOI SRAMs, PBTI dominates the degradations in read...

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