This work presents a CMOS integrated interface circuit (IIC) enabling highly efficient energy transfer from piezoelectric generators (PGs) to a storage element, e.g. a large capacitor. Due to the low power consumption of 4.7 μW assuming a supply voltage of 2.5 V, the IIC can be supplied totally by the storage capacitor. The storage capacitor can be passively charged via a bypassing circuit if i...

This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to classAB linear operation and the virtual transistor technique to lower the effective threshold voltages...

This paper describes design of high energy efficiency 32 bit parallel processor core using instructtion-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converte...

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pos...

In this paper a novel common mode separation technique for implementing fully differential current buffers is introduced.  Using the proposed method two high CMRR (Common Mode Rejection Ratio) and high PSRR (Power Supply Rejection Ratio) fully differential current buffers in BIPOLAR and CMOS technologies are implemented.   Simulation results by HSPICE using 0.18μm TSMC process for CMOS based st...

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel postsilicon tuning methodology to scale optimum voltage and frequency “dynamically”. The proposed design technique will use our PVT sensor circuits to monitor the varia...

As the technology is continuously scaled, leakage currents become a major contributor to the total power dissipation. A reduction in power supply voltage is necessary to reduce dynamic power and avoid reliability problems in deep sub-micron (DSM) regimes. Threshold voltage reduction accompanies supply voltage scaling to maintain the performance, but it exponentially increases the subthreshold l...

This paper describes the development of high voltage power supply for electro-optics applications. The power supply consists of MOSFET driver, voltage multiplier circuit and voltage controller. A single timer 555 generates 1.3 kHz square pulse to drive the power MOSFET that connected to a standard step up transformer. By using voltage multiplier technique, the output from secondary transformer ...