The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standa...

The Network-on-chip (NoC) designs consisting of large pack of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically possible nowadays. But, the communication between the IP Cores is the main issue in recent years. This paper presents the design of a Code Division Multiple Access (CDMA) based wrapper interconnect as a component of System on programmable chip (...

Network-on-Chip (NoC) replaces the traditional bus-based architecture to become the mainstream design methodology for future complex System-on-Chip (SoC). It introduces the principles of packet switching and interconnection network into SoC design, and achieves much better performance for its high bandwidth, scalability, reliability, etc. However, thermal problem, such as regional temperature d...

Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability. The chip scenario has the particularity that is static, and the multipath can be known a priori. Within this context, we propose in this paper ...

Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is pro...

In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC architecture design for its simple topology an...

System on Chip (SOCJ design in theforthcoming billion transisror era will involve the integration of numerous hererogeneous semiconductor intellectual proper@ ( I f ) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in rhe range of 50-100 nm arise from non-scalable global wire delays, failure ro achieve global synchronization, errors due ...

Most of today's SOCs (Systems on Chips) are made of manufactured IP's interconnected through complex networks. The IP's have ordinarily been validated by various techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of such Networks on Chips by means of a mechanized proof to...

Networks-on-Chip is emerging as a communication platform for future complex SoC designs, composed of a large number of homogenous or heterogeneous processing resources. Most SoC platforms are customized to the domainspecific requirements of their applications, which communicate in a specific, mostly irregular way. The specific but often diverse communication requirements among cores of the SoC ...