1. Holey Silicon fabrication The HS ribbons used for transport measurements are patterned by optical lithography and then released from SOI substrate (Soitec Inc.) by hydrofluoric acid vapor etching. The SOI wafer consists 100 nm device layer (<100>, 14-22 Ω·cm, phosphorus doped) with 200 nm buried oxide layer. Holey structure is fabricated by DRIE through thin chromium mask (~5 nm) converted f...

La musique est une activité productrice de sons, prenant place dans un environnement où se croisent pratiques tangibles (travail l’instrument, écriture musicale, matérialité du spectacle) et intangibles (propriétés sonore, singularité l’expérience volatilité la performance). Cet article propose d’explorer façon dont ce croisement contribue à revisiter tradition culturelle, ici celle des défilés...

In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han–Carlson ALU, operating at 482 ps in 1.5 V, 0.18m bulk CMOS; 2) direct port of this ALU to 0.18m partially depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel deep-stack quaternary-tree architecture; 4) margining for max-delay pushout due to reverse body bias in SOI designs; and 5) performance scal...

Silicon-on-insulator ~SOI! has proven to be a viable alternative to traditional bulk silicon for fabrication of complementary metal–oxide–semiconductor devices. However, a number of unusual phenomena with regards to diffusion and segregation of dopants in SOI have yet to be explained. In the present study, SOITEC wafers were thinned to 700 and 1600 Å using oxidation and etching. Ion implantatio...