In this paper the problem of accommodating particular analog system models, with emphasis on interconnection's representation, with discrete event simulators, and particularly with VHDL circuit descriptions, is discussed and a solution is proposed. The results can be successfully used for VHDL modeling and simulation, but they are implementation independent.

This paper describes an ongoing high level synthesis project using dependence ow graphs as intermediate form. This HLS system takes a behavioral description written in a subset of VHDL and generates an RTL VHDL description that implements the design. We use dependence ow graphs as an intermediate form. We only describe the compilation part of the HLS system and dependence ow graphs.

LibQA is a quality assurance tool for VHDL synthesis and simulation models which also performs timing characterization. The synthesis model is translated into an FSM, then graph exploration generates stimuli for VHDL and electrical simulation. Function, propagation delay, timing constraint violation, and hazard response are all tested.

ID#413 – Author: Sreeram Rajagopalan 2 1. ABSTRACT PSpice A/D is a simulation package that is used to analyze and predict the performance of analog and mixed signal circuits. It is very popular especially among Printed Circuit Board (PCB) engineers to verify board level designs. However, PSpice A/D currently lacks the ability to simulate analog components connected to digital circuits that are ...